LEE- Elektronik Mühendisliği Lisansüstü Programı

Bu topluluk için Kalıcı Uri

http://hdl.handle.net/11527/19263

Gözat

3D-printed actuator-based beam-steering approach for improved physical layer security in visible light communication

(Graduate School, 2022-09-05) Erdem, Mehmet Can ; Ferhanoğlu, Onur ; 504201223 ; Electronics Engineering

In this thesis, the design, manufacturing and implementation of a 3D-printed lens scanner-based beam-steering are presented for use in visible light communication (VLC) applications. The scanner, measuring 5 x 5 cm, is designed for low-cost 3D printing with fused deposition modeling using polylactic acid (PLA). The scanning is facilitated through electromagnetic actuation of the lens frame, carrying a conventional 25 mm lens in two nearly orthogonal directions. The serpentine spring that connects the lens frame to the external frame is tailored to offer similar spring constants in the directions of actuation, and minimal (< 1.5 mm) sag due to the mass of the lens. The manufactured actuator was integrated on a miniaturized VLC test-bed (70 cm x 40 cm x 40 cm). Using the test-bed, the applied voltage vs. beam displacement behavior of the actuator was characterized in the lateral plane, and beam-steering on a moving target was demonstrated with face-recognition feedback. The proposed scheme was targeted to offer an improved security measure in VLC through tracking the legitimate receiver (i.e. via face recognition) and using the feedback to steer the focused light onto the targeted device. The joint use of focusing and steering features allows for the legitimate receiver to roam within the room while enjoying the improved secrecy due to focused light. The secrecy capacity for the demonstrated approach was also calculated, which compares favorably to a number of jamming, spatial modulation and beam-forming counterparts. The presented actuator can be used with larger room dimensions, yet up-scaling to larger illumination units will require the use of a lens having a smaller focus to achieve a larger total steering angle. This thesis is composed of five different chapters. The concepts of visible light communication and light fidelity (Li-Fi) are introduced with a thorough literature review in the first chapter, while the techniques used in the thesis are also defined and presented. In the second chapter, the design of the actuator is described through definite computer-aided design (CAD) models and finite element analysis (FEA) simulations, while the experimental setup is also presented. Meanwhile, the demonstrations and the measurement results from the beam-steering operation of the actuator are presented in the third chapter. Then, the discussion section, based on the secrecy improvement through the use of the actuator and the up-scaling of the actuator to real-world dimensions, is presented in the fourth chapter. Finally, the fifth chapter presents the conclusions and further future work based on the actuator. Also, the details regarding the experiments conducted in Chapter 3, some of the designs of the actuator that were changed in order to obtain the final prototype and some discussion based on the mechanical stress on the actuator caused by the weight of the lens are presented in the Appendix section.
4 channel configurable constant-current/voltage mode biphasic implantable neurostimulator ASIC with channel centric active charge balancer

(Graduate School, 2022-03-02) Cakalı, Anıl ; Karalar, Tufan Coşkun ; 504161229 ; Electronics Engineering

Electrical stimulation is a technique that let inhibition or exhibition neuron activities with charge injection to a target tissue. Neural stimulators are used as a treatment method for diseases and the restoration of dysfunctional organs. Sacral Nerve Stimulation that is used for the treatment of bladder and urinary functions, Deep Brain Stimulation (DBS) that is used for the treatment of diseases such as Parkinson's disease, epilepsy, tremor, depression, and obsessive-compulsive disorder, Spinal Cord Stimulation that is used for the treatment of chronic pain syndrome, Retinal Stimulation that is used for recovering visual functions and Cochlear Stimulation that is used to recovering of hearing functions are some of the application fields of electrical/neural stimulation. Considering application fields, most neurostimulator/neuromodulation devices are implanted in the human body. These devices are battery-powered devices that have long battery life, because of that an Application Specific Integrated Circuit (ASIC) is needed for implantable applications considering application specifications like target nerve, power consumption and output properties. Neurostimulators interface with target neurons by using electrodes. Charge accumulation on an electrode-tissue interface may cause Ph variation of electrolyte, toxic surface creation between electrode-tissue interface and variation of electrode-tissue impedance. Most importantly, it may cause permanent nerve damage. Using biphasic stimulation and active charge balancer structure together is the preferred method to achieve ideally zero net charges on the target tissue. Constant-current stimulation, constant-voltage stimulation or constant-charge stimulation methods are presented in the literature. Constant-current stimulation is the safest stimulation method. Ideally, zero net charge on tissue may be achieved by controlling anodic and cathodic current amplitudes and durations in a biphasic manner. For constant-voltage stimulation, the amplitude of current that flows through the electrode-tissue interface is determined by the impedance of the electrode-tissue interface. Due to that reason, it is not easy to control transferred charge to tissue. Constant-charge stimulation is a useful method to achieve charge balancing by using switch-capacitor structures. The disadvantage of constant-charge stimulation is that it needs larger capacitors that cause some difficulties with on-chip implementation. In literature, neurostimulator ASICs are designed for only constant-current mode stimulation or only constant-voltage mode stimulation. Similarly, most charge balancer circuits are designed for just constant-current mode stimulation or constant-voltage mode stimulation. In this work, a novel active charge balancing scheme that works with both constant-current mode and constant-voltage mode for monopolar/bipolar/tripolar/quadripolar electrode polarities is proposed. Furthermore, a novel channel circuit and novel channel centric active charge balancer circuit topologies that support both constant-current and constant-voltage stimulation mode in the same structure are developed. Constant-voltage mode stimulation is considered the standard technique of DBS applications for a long time. On the other hand, constant-current mode stimulation is emerging as an alternative solution for DBS applications. Supporting both constant-current mode and constant-voltage mode with active charge balancing makes this work appropriate for DBS applications. The purpose of this work is to increase the flexibility and safety of neurostimulators because this work allows switching stimulation mode after surgery and supplies active charge balancing for both stimulation modes for safety. Neurostimulator ASIC is constructed by 4 channels. Each channel consists of N-Block, P-Block and Channel Centric Active Charge Balancer. Each channel is configurable to supply ground, 10 V, 0-1 mA configurable sink current or 0-1 mA configurable source current in constant-current stimulation mode. Each channel is configurable to supply ground, 10 V, 1-5 V configurable low voltage or 5-9 V configurable high voltage in constant-voltage stimulation mode. N-Block circuit is designed to supply ground, 0-1 mA configurable sink current or 1-5 V configurable low voltage. P-Block circuit is designed to supply 10 V (as VDD), 0-1 mA configurable source current or 5-9 V configurable high voltage. Stimulation period, anodic phase time and interphase delay time are configurable parameters. Cathodic phase duration is not configurable because it is controlled by using outputs of Channel Centric Active Charge Balancer asynchronously. N-Block and P-Block circuits are similar to each other and complementary structures. The supply voltage of the stimulator circuit was chosen as 10 V to prevent headroom problems. Considering high voltage supply requirements, the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 um Bipolar-CMOS-DMOS (BCD) technology process was chosen. Relatively high biasing currents and enable/disable circuits were used for analog blocks to achieve higher performance with lower power consumption. The actual channel current is estimated by using differences of internal currents. Internal currents are mirrored to channel centric active charge balancer circuit to estimate channel current and use it for charge balancing. Timing setting resolution was chosen as 1 us. All analog blocks that are used in N-Block and P-Block were designed in Cadence Virtuoso considering timing, voltage and process constraints. DC, AC, transient and stability simulations were run to verify analog subblocks with Cadence Spectre. Transient simulations were run to verify constant-current stimulation mode and constant-voltage stimulation mode behaviors of N-Block and P-Block. Maximum current error results for constant-current stimulation, maximum voltage error results for constant-voltage stimulation and channel current estimation error results for both stimulation modes are given as simulation results. Channel centric active charge balancer was designed with Cadence environment. Transient simulations were run considering stimulation duration and current amplitude boundaries to verify functionality and determine performance with Cadence Spectre. Charge errors are presented as simulation results. Register Transfer Level (RTL) design of the stimulator controller was designed with Verilog Hardware Description Language (HDL). Synchronous state machines are used to implement the stimulator controller. Asynchronous digital circuits are used to handle outputs of active charge balancer circuits. The stimulator controller was synthesized by using Cadence Genus tool. Place and route process was performed by using Innovus tool. Digital blocks were integrated with analog blocks in Cadence Environment and Analog-Mixed Signal (AMS) simulations were run to verify the behavior of the neurostimulator ASIC for constant-current and constant-voltage stimulation modes with random test vectors. As a conclusion, 4 channel configurable constant-current/voltage mode biphasic implantable neurostimulator ASIC with channel centric active charge balancer was verified by using AMS simulations for both constant-current and constant-voltage stimulation modes. AMS simulation results show that the ASIC works functional and the proposed channel centric active charge balancing scheme is verified for both stimulation modes.
8 Gbps LVDS transmitter design in 22 nm FD-SOI for high speed chip-to-chip communication interfaces

(Graduate School, 2024-06-04) Kurt, Alper ; Tekin, Ahmet ; 504211235 ; Electronics Engineering

In recent years, tremendous advancements in the processing speed of microprocessors, motherboards, optical transmission links, and routers have expanded the off-chip data rates. The increasing demand for data bandwidth across electronic systems has led to significant innovations in wireline input/output (I/O) drivers. Various standards have been created by many institutions to manage the difficulties of high-speed wireline data transmission. The aggressive technology scaling not only increased the interest in I/O speed but also it additionally contributed noticeably to the enhancement in data rate and power efficiency of the wireline links. Even though the I/O data rates and data processing power have been improved by the technology scaling, the bandwidth of the copper links has not been scaled in the same manner. Therefore, the requirement for advanced equalization techniques has emerged in recent years to eliminate the corrosive effect of the channel such as inter-symbol interference (ISI) emerging at high frequencies. LVDS standard have been very popular among other communication standards due to its low power consumption, high noise immunity, high speed point-to-point data transmission, and good electromagnetic interference performance. LVDS is configured as a switched-polarity current generator. Optimum line impedance matching is achieved due to differential termination resistor at the receiver end of the system. Since LVDS transmits differential data, crosstalk and robustness of the link to common mode noise is extremely enhanced. The received digital data is represented with analog voltage swing at the output of the LVDS, which improves the data rate and also reduces power consumption. The channel is the physical medium that signal passes through from transmitter side to receiver side. Transmitted signal travels through various traces before reaching its destination. With the increase in frequency, line attenuation of this channel increases due to dielectric loss and skin effect. The channel behaves like a low pass filter which deteriorates the signal quality. first pre-cursor and post-cursor samples become very large due to Pulse dispersion from low-pass filtering, which makes detecting the bits that are transmitted in a sequence. This effects also generates intersymbol interference (ISI), which is interference of the transmitted symbol with the subsequent symbol due to distortion at high data rate. As a result, to overcome the corrosive effects of the channel equalization is needed. In general, pre-emphasis technique is used in transmitter side for channel equalization. In this thesis, 8 Gbps Low-Voltage Differential Signaling (LVDS) transmitter having controllable pre-emphasis and inductive peaking is designed for high speed chip-to-chip communication links. The transmitter system contains of pre-driver, core LVDS driver with Common Mode Feedback (CMFB) Amplifier, delay lines, auxiliary pre-driver and Pre-emphasis blocks. It has 1.225 V output common mode voltage which is adjustable between 0.98 V and 1.330. The output swing amplitude is between 230 mV and 350 mV. It consumes 20.248 mW power at 8 Gbps data rate which yields 2.531 pJ/bit energy efficiency. LVDS transmitter is implemented in 22 nm Fully Depleted Silicon on Insulator (FD-SOI) technology and the layout occupies 0.036 mm2 area including layout.
A robust framework covering measures developed using EVM metric against jamming attacks in next-generation communication systems

(Graduate School, 2024-08-07) Örnek, Cem ; Kartal, Mesut ; 504182213 ; Electronics Engineering

In the face of escalating threats posed by malicious jamming in next-generation communication systems, this thesis presents a comprehensive framework comprising jamming signal detection, jamming signal classification, jammer localization, and two anti-jamming strategies to address these challenges effectively. The proposed error vector magnitude vs. resource block (EVM vs. RB) methodology for jamming signal detection, unlike traditional approaches commonly use received signal strength (RSS) and bit error rate (BER), examines the effects of jamming signals on IQ symbols using the EVM metric. Our methodology, which is able to capture even small changes imposed by jamming signals on IQ symbols, provides significant advantages in terms of sensitivity compared to the conventional approaches. Moreover, the proposed methodology has a low-complexity of the order of O(N), which is especially important for next-generation communication systems known for their strict latency requirements. By utilizing IQ symbols that are natively generated in the data transmission system, our methodology seamlessly integrates into existing 5G and LTE systems without imposing additional overhead, facilitating practical deployment in real-world scenarios. RBs represent the frequency domain for next-generation wireless communication systems and the proposed methodology measures the EVM for each RB in the received signal. In this way, our approach not only detects jamming signals but also provides vital frequency information associated with the jammer. This information enhances counteraction capabilities, enabling targeted responses to mitigate the impact of jamming attacks. Furthermore, the proposed method demonstrates stability across varying system parameters, including modulation type and code rate, thereby contributing to adaptability in dynamic communication environments. The effectiveness of the proposed detection methodology is validated through extensive theoretical analysis, simulation studies, and laboratory experiments. Theoretical analyses substantiate the advantages of our approach, reinforcing its validity and reliability. Simulation results showcase the robustness and stability of our method across diverse scenarios, highlighting its practical utility in real-world applications. Laboratory experiments provide empirical evidence of its effectiveness, further validating its potential for deployment in operational communication systems. Beyond the jamming signal detection, our jamming signal classification methodology offers a comprehensive solution to accurately characterize and classify various jamming signals by utilizing Symbol-RB-EVM which is another measurement we developed. The Symbol-RB-EVM measurement is created by accumulating the EVM vs. RB data obtained for each OFDM symbol time into a matrix and provides a nuanced understanding of jamming signal behavior across time and frequency domains. Unlike traditional measurements such as spectrogram, RSS, and BER, the proposed measurement offers superior sensitivity and specificity in capturing the intricacies of jamming signals. After creating the dataset using the Symbol-RB-EVM results, we take advantage of machine learning algorithms for jamming signal classification. Thanks to the fact that Symbol-RB-EVM efficiently provides useful features of jamming signals, the proposed methodology enables precise classification of jamming types with high accuracy, thereby minimizing false alarms. This property of Symbol-RB-EVM also enables lower complexity machine learning methods to produce successful results even with minimal training data. Add to this the fact that Symbol-RB-EVM is computed with low computational complexity (O(N)), and we can say that the proposed methodology is in a very valuable position in terms of overall complexity. Extensive simulations demonstrate the superior performance of the proposed metodology in accurately characterizing diverse jamming signal types across varying scenarios and environmental conditions. In addition to the detection and classification, the EVM metric is also considered to provide effective results for jammer localization problem. The localization process begins with the detection of jamming signals using the EVM vs. RB methodology. EVM contours are then drawn on the map using the EVM data acquired from user equipments (UEs). In this approach, which has a range-free feature, the contours are concentrated towards the jammer source, providing a coarse estimate of the location of the jammer. WhentheUEdensitysurroundingthejammerissufficiently high, accurate localization can be swiftly achieved using these contours alone, eliminating the need for further operations. However, in cases where the UE density is not sufficient for an accurate localization, we take our methodology to a hybrid structure by also using Time Difference of Arrival (TDOA), a range-based technique, to improve localization accuracy. With the help of the coarse location information from the EVM contours, the right one is selected quickly among the sensitive solutions offered by the TDOA. Thanks to such an innovative approach, the quickness of the range-free technique and the high accuracy of the range-based technique are combined. Extensive simulations demonstrate the localization success of the proposed methodol ogy across diverse network densities and environmental conditions, underscoring its robustness and reliability in real-world deployment scenarios. By offering both high accuracy and low complexity, our methodology promises to bolster the resilience of 5G networks against malicious jamming attacks, ensuring uninterrupted communication services and safeguarding critical data transmission pathways. Effective solutions presented in the fields of jamming signal detection, classification and jammer localization encourage us to develop successful anti-jamming solutions. The first anti-jamming proposal provides a robust method designed to protect next-generation communication systems from malicious jamming. At the beginning of this methodology is the identification of RBs affected by jamming attacks through the EVM vs. RB measurement. By leveraging this measurement, which provides insight into the frequency domains targeted by jammers, our methodology effectively discerns clean RBs from those under jamming influence. Building upon this insight, we propose an RB sharing strategy aimed at optimizing resource allocation and protecting UE from jammer interference. The strategy prioritizes the allocation of clean RBs to UEs closest to the jammer, thereby isolating their signals from jamming attacks and ensuring uninterrupted communication. Acknowledging the finite nature of RB resources, our research endeavors to assess jammed RBs and allocate them to UEs farthest from the jammer whenever possible. Alternatively, we are also investigating data rate reduction strategies that can be realized for these RBs in order to increase their resistance to jamming. Key to the success of our methodology is its low-complexity decision-making process, which eliminates the need for extensive training and ensures rapid response capabilities—critical attributes in the context of next-generation communication systems characterized by low-latency requirements. Moreover, our approach seamlessly integrates with existing system architectures, leveraging IQ data obtained from the inherent system flow for necessary EVM measurements. Simulation results underscore the efficacy of the proposed methodology in maintaining maximum UE throughput, even in the face of sustained jamming attacks. By optimizing RB resource utilization and minimizing disruptions caused by jamming interference, our approach promises to bolster the resilience of next-generation communication systems against evolving threats and ensuring uninterrupted service delivery. Our second anti-jamming proposal introduces a novel methodology engineered to confront the challenges posed by malicious jamming attacks head-on. At its core lies a sophisticated approach that harnesses transmitted and received IQ symbols to train a linear regression algorithm, enabling the system to adapt and neutralize the disruptive effects of jamming signals on the IQ symbol packets. Utilization of the EVM metric gauges the training performance of the linear regression algorithm. Through an iterative process, the algorithm assimilates the impact of jamming signals on IQ symbols, effectively deciphering their disruptive effects and restoring communications for jammer-occupied resources. One of the key strengths of our methodology lies in its adaptability to diverse jamming signals, ensuring robust protection against a wide range of jamming tactics. By efficiently restoring communications for jammer-occupied resources, our approach minimizes the impact of jamming attacks on network performance, ensuring uninterrupted service delivery for end-users. Moreover, the low-complexity implementation is facilitated by leveraging linear regression and EVM techniques. Theoretical analyses and simulation results confirm the effectiveness of the proposed methodology and underline its potential to increase the resilience of communication infrastructures against malicious interference.
Ac-coupled supply modulator desıgn ın 130 nm PD-SOI technology

(Graduate School, 2023-06-14) Barin, Furkan ; Tekin, Ahmet ; Zencir, Ertan ; 504201216 ; Electronics Engineering

High peak-to-average values (PAPR) of modern telecommunications standards tend to drop the efficiency of the power amplifiers. The drop in efficiency causes excessive power consumption, which leads to a shortened battery life for mobile systems. As a result, envelope-tracking supply modulator (ETSM) systems are developed to improve power amplifier efficiency by varying their supply voltage. There are different envelope-tracking supply modulator topologies in the literature that combine different amplifier structures with each other. The most popular topologies can be considered hybrid topologies, which take advantage of using two amplifiers in parallel with each other. This hybrid structure allows high-frequency components to be provided by the linear amplifier while low-frequency power is provided by a highly efficient switching amplifier. The linear amplifier is generally designed with a Class AB output driver, which increases the driving capability and reduces the power consumption of the linear amplifier. A buck converter is mostly used as a switching amplifier to generate DC current for the load. In the literature, a hysteretic control loop is commonly used to control the buck converter with the linear amplifier, and an additional dc-dc converter is added to control the supply voltage of the linear amplifier. To improve efficiency, AC-coupled hybrid topologies are introduced to lower the power consumption of the linear amplifiers. In this thesis, an AC-coupled hybrid ETSM is designed for 5G cellular vehicle-to-everything (C-V2X) systems that support up to 40 MHz of baseband bandwidth. The system consists of a proposed operational amplifier, a switching amplifier, a current-mode hysteretic buck converter to control the supply of the linear amplifier, a proposed zero-current detection (ZCD) current to detect the reverse current flowing through the inductor, and low-dropout regulators (LDO) for supplying the internal analog circuits. The ETSM is implemented in a 130 nm partially depleted (PD) silicon on insulator (SOI) process, and the die size is 3.051 mm2.
Analysis and design of cryogenic bulk-driven analog integrated circuits

(Graduate School, 2022) Ormancı, Mehmet Aytuğ ; Yelten, Mustafa Berke ; Kaçar, Fırat ; 737869 ; Electronics Engineering Programme

Today, exponentially increasing studies such as quantum electronics, asteroid and planet observations, and even space mining have increased the need for electronic circuits that can operate under extreme conditions without error. Circuits that can operate without consuming much power, especially in space conditions, allow for more or uninterrupted observations and measurements. The operating conditions for circuits operating in space are extreme. It is essential that the designs made for these circuits, which must operate in both high radiation and very cold conditions, produce accurate results because space is still a very costly environment in terms of research and observation costs. In this case, it is important to correct the errors in the designs at the simulation stage. The concept of a cryogenic environment defines the temperature values of 120 K (−153 ℃) and below, although the exact limits are not clear. This is because this temperature includes the boiling points of the main atmospheric gases. The design at cryogenic temperatures is indispensable for space exploration and quantum computers. Liquid nitrogen environment (LNT) is the most common method used to model cryogenic environments on the earth's surface and in laboratories and to develop circuits operating in space conditions. Nitrogen, which has a boiling point of approximately 77 K, contains most of the critical situations that electronic circuits encounter in space conditions. The operating range for integrated circuits traditionally based on common design models such as BSIM is between −55 ℃ and +125 ℃. However, when the design results made with these models are examined, it is observed that the error rate increases even moving away from the room temperature. This makes it inevitable to use new models for cryogenic conditions. The cryogenic modeling process used in this thesis is based on the logic of recalculating and replacing temperature-sensitive parameters and sub-parameters in the BSIM by using a MATLAB environment with a new algorithm. In this way, the margin of error in the experimental measurements is considerably reduced and this environment is accurately simulated in computer-aided programs. In experiments with many transistors in the cryogenic environment, it has been observed that the threshold voltage increases, but the current flowing capacity of the transistors increases as the mobility of the carriers rises. In addition, in the theoretical and practical studies, the linear reduction of thermal noise, which is seen as the main source of the noise in transistors, with temperature is promising results for the designers. With the developing electronic technology, the use of portable devices and biomedical sensors has become quite common. This brings the need for more efficient use of batteries, which cannot develop at the same rate. For this reason, the electronics industry turns to devices that work with less than 1 V power supply and consume very little power. One of the circuit design methods with a very low power supply is bulk-driven (BD) structures. Thus, when the gate terminals are biased with a DC voltage that creates a channel between the source and the drain, the current passing through the channel can be manipulated by the input signal applied from the bulk. In terms of the circuit designs, this method means removing the threshold voltage from the signal path. The most important advantages of the bulk-driven transistors can be shown as having much more linear transconductance and much less power consumption. In addition, without using n-channel and p-channel transistors together, the input common-mode range (ICMR) and output swing can be rail-to-rail. However, driving the transistor from the bulk also brings some disadvantages. The most important issue is the bulk transconductance is quite low compared to the gate-driven counterpart. Although it is theoretically possible to increase, it can activate the parasitic Bipolar Junction Transistors (BJT) in the structure and damage the chip. Also, low transconductance increases the noise factor of transistors. Another detriment is the high capacitive effects on the body. These effects greatly reduce the transition frequency of transistors. Another low power circuit design method is to operate the transistors in the subthreshold region. Transistors enter the subthreshold saturation region between 3 and 4 times their thermal voltage and can operate with low power supplies. Operational transconductance amplifiers (OTA), which are one of the indispensable building blocks of analog designs, are frequently used in analog signal processing, thanks to the high-level linear transconductance and stable high frequency performance. In this study, a three-stage OTA is designed in which all transistors operate in the subthreshold saturation region. It consists of an input stage based on non-tailed differential amplifiers, a second stage with a common-source amplifier, and a class AB output stage. The input stage provides high ICMR and 36 dB DC gain. The bias current of this structure was calculated as 8 nA using thermal noise and dynamic range in the voltage follower configuration.
Approximate artificial neural network hardware aware synthesis tool

(Lisansüstü Eğitim Enstitüsü, 2021) Nojehdeh, Mohammadreza Esmali ; Altun, Mustafa ; 692582 ; Elektronik ve Haberleşme Mühendisliği

In the previous decade, artificial neural networks (ANNS) have attracted considerable attention from researchers in many areas and have become a favorite method; from business to aerospace applications. We live in the information age where this information feeds artificial intelligence (AI). According to Forbes' estimate, over the last two years alone 90 percent of the data in the world was generated. At first glance, processing more information may seem like a dissipation of more power in central processing units(CPUs) and graphic processing units (GPUs) or spending more time to obtain the results, but for the portable systems due to limitations in battery capacity, power, and hardware area limitations, different concerns emerge. For example, less consumption of energy is vital to extend the battery supporting time for mobile devices. The problem starts to be bold when software engineers regardless of the hardware sources (especially for portable devices) develop different ANNs architecture, where they intend to achieve a network with the best performances. Similarly, hardware engineers' AI knowledge is limited and any change within hardware design in lack of this knowledge may yield a catastrophic defect in the expected performance. As a result, this uninformed state yields a gap between the hardware and software sides of ANNs. The emerged gap provides a pitch to hardware and software researchers to play their best performance, where more information about the rival side makes their performance more eye-catching. By obtaining this gap, the co-design method or hardware-aware training methods become prevalent recently. The object of this dissertation is also to develop a methodology to realize the ANNs with minimum hardware cost by regarding the software performance. Limitation in hardware cost, consumed energy, and dissipated power for devices leads designers to find new architectures and approaches. Approximate computing is one of them, where this method is an useful technique for error essence systems. By leveraging the approximate level, a trade-off between the output accuracy and hardware cost is attainable. For example, assume a 1-bit exact adder costs 18 transistors, and by removing 3 transistors, a new approximate adder by 15 transistors is achievable, but the new approximate adder generates inexact results when the input is $(0,0)$, and suppose that the results for the rest set of the inputs$((0,1),(1,0),(1,1))$ are correct. Therefore, the approximate adder saves 3 transistors at the cost of 1 inexact result. Generally, approximate computing is apple of designers' eye in applications with error tolerance capability, consequently, error tolerance inherence of ANNs nominates approximate computing as a potential method to reduce the hardware complexity of ANNs. Since multipliers and adders are fundamental building blocks of ANNs, in this thesis, by introducing novel approximate multipliers and adders we replace them with exact adders and multipliers. As mentioned earlier, approximate computing is a trade-off between accuracy and hardware cost, to adjust this trade-off, we synthesized the proposed approximate blocks based on the desired error metric. Also, we proposed an equation to calculate the mean absolute error of the introduced approximate multiplier and adders. Based on our best knowledge, the proposed approximate blocks are the only ones which are synthesized based on the mean error value. In next step, we introduced a new error metric called the approximate level to evaluate the performance of the proposed approximate blocks in ANNs. On the other hand, ANNs are made up of a lot of multipliers and adders, where the search space for the best combination of these blocks grows with the increase of bit-width or neuron numbers. To tackle this problem and by exploiting the proposed error metric, we introduce a new search algorithm to find the appropriate combination of the approximate and exact versions of the arithmetic blocks by taking into account the expected accuracy of ANNs. Also, in this thesis we realized ANNs under different synthesis techniques to obtain the pros and cons of each approach. Since the parallel architecture requires a large area we considered the time-multiplexed architecture as the main architecture method, where computing resources are re-used in the multiply-accumulate (MAC) blocks. As an application, the MNIST and Pen-digit database are considered. To examine the efficiency of the proposed method, various architectures and structures of ANNs are realized. Our experimental results show that exploiting the proposed approximate multipliers yields smaller area and power consumption compared to those designed using previously proposed prominent approximate multipliers. Also, according to these results, concurrent use of approximate multipliers and adders provides remarkable results in terms of hardware cost, where we obtain $60\%$ and $40\%$ reduction in energy consumption and occupied area of the ANN design with the same or better hardware accuracy compared to the exact adders and multipliers. To demonstrate the proposed method's scalability, we propose an efficient method to realize a convolution layer of convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convolution operations.
Artificial neural network based electrical machine fault classification on FPGA

(Graduate School, 2024-12-17) Aydın, Mert Yaşar ; Yalçın Örs, Sıddıka Berna ; 504211216 ; Electronics Engineering

Electrical machines and drives play a critical role in modern society, spanning industrial equipment to renewable energy production. The reliability and efficiency of these systems depend on continuous performance monitoring and the early detection of potential issues. Condition monitoring systems are essential for evaluating the performance of machines and detecting potential faults early, thereby reducing unexpected downtimes and maintenance costs. Traditional fault detection methods include vibration analysis, thermography, and oil analysis. Vibration analysis is used to identify mechanical issues, while thermography can detect overheating that may indicate electrical or mechanical problems. The integration of artificial intelligence (AI) and machine learning techniques has significantly enhanced fault detection capabilities. AI techniques such as artificial neural networks (ANN) and support vector machines (SVM) can process large datasets to predict potential faults in advance. This thesis aims to develop and implement an ANN-based fault diagnosis system for electrical machines on an FPGA platform. The system will leverage the high-speed processing and parallel computing capabilities of FPGAs to achieve real-time fault detection and diagnosis. Additionally, this method will be tested with different datasets to evaluate its generalizability. The thesis comprises two main sections: deep learning and FPGA applications. The first section describes the dataset used, data processing, and the development of the CNN architecture. The second section discusses the implementation of the CNN model on FPGA using VHDL. Experimental results are presented in the final section. In the deep learning section, a CNN-based fault detection model has been developed for ensuring the reliable operation of electrical machines. The dataset used consists of vibration signals obtained from the MAFAULDA database. The data were used to train and test the CNN model, with performance evaluated based on accuracy, precision, recall, and F1 score. The ability of CNNs to learn local patterns and features makes them particularly effective for fault detection. The FPGA application section covers the implementation of the CNN-based fault detection system on FPGA. Convolution_1D, Convolution_1D_Middle, Convolution_1D_No_MP, and Dense layers were developed using VHDL. Real-time fault detection was performed using the Nexys A7 development board. The parallel processing capabilities of the FPGA allowed for high-speed computations, making the system suitable for real-time applications. This implementation efficiently handles large volumes of data, ensures low latency, and maintains high accuracy. When developing a CNN-based fault detection system using VHDL, optimizing the layers and processes is crucial. The Convolution_1D, Convolution_1D_No_MP, and xx Convolution_1D_Middle layers perform 1D convolution operations on the input data using predefined kernels. The Convolution_1D layer extracts fundamental features from raw sensor data, while the Convolution_1D_No_MP layer maintains higher resolution for detailed analysis. The Convolution_1D_Middle layer further refines the features, ensuring high accuracy in fault detection. The Dense layer processes these features into the final classification result. The TOP_CNN module integrates all layers, managing the data flow and producing the final fault classification result. In conclusion, a CNN-based fault detection system has been developed and implemented on FPGA. The system significantly enhances the reliability and efficiency of electrical machines. Future research will involve testing this method with broader datasets and different application areas to further evaluate and improve its effectiveness. This work contributes to the implementation of proactive maintenance strategies in industrial processes, ensuring operational excellence of machinery
Bandgap reference and low dropout voltage regulator desıgn for capsule endoscopy system

(Graduate School, 2022-06-01) İnam, Benan Beril ; Yelten, Mustafa Berke ; 504191204 ; Electronics Engineering

For the last 40 years, there have been many advancements in biomedical systems as there is a huge demand for them. A capsule endoscopy device is one of the biomedical systems which is used for the imaging of the gastrointestinal system. Endoscopic procedures require two operations because when the procedure starts from the esophagus it can only reach until duodenum, however imaging of the small bowel can be only accessed from the anal cavity. This operation is highly uncomfortable for the patient since the diagnosis of the entire gastrointestinal system requires two endoscopic procedures. To make this operation more comfortable for the patient, capsule endoscopy is developed. The capsule endoscopy system includes a laser source and a laser driver to process the information coming from the source and a transmitter system to transmit the processed data. The transmitter involves an analog to digital converter, transimpedance amplifier, power amplifier, and a phase generator. A single battery is used to supply voltage for all of these mentioned circuits. The battery input voltage of the system decays with time and to increase the lifetime of the capsule it is essential to design a power management unit. This power management unit involves a regulator to create supply voltage for chip blocks and a reference generator to obtain process-voltage-temperature independent reference. For the regulator, a low dropout regulator is chosen as they do not have ripple at the output voltage as in switching regulators which makes them less noisy. Noise is an important parameter because the input signal is low and any input voltage may affect the operation of the circuits. Traditional LDOs require a large off-chip capacitor at the output to create a right half plane zero and stabilize the circuit. However, the capsule is strictly limited in the area hence a cap-less LDO is designed. To enhance the transient performance after removing the output capacitor, a dynamic bias circuitry is added to the design. Output voltage only changes 6 % with process-temperature-voltage corners. Load and line transient results show that even though the input voltage or output load changes with time, the circuit can still regulate the output voltage. To obtain reference voltages for the blocks, a bandgap reference voltage generator is designed. In this design, two different design structures are used to achieve temperature independence. Both MOS and bipolar transistors are employed for this purpose. Design with MOS transistors advantages from operating in the subthreshold region hence supporting lower supply voltages however it has a larger variation at the output due to threshold voltage change over corners. Bipolar transistors benefit from less PVT variation however their performance degrades with lower supply voltages and high temperatures. To use two different characteristics of both designs, a system that switches to better performing structure is built. A comparator is designed to detect temperature and supply voltage. In this system, reference with bipolar transistors operates when the input voltage is higher than 2.8 V and at lower temperatures, and reference with MOS transistors starts to work when the input voltage is lower than 2.8 V and at higher temperatures. To further reduce the variation of the design with MOS trimming structure is implemented to the output resistor and variation decreased from 15% to 5%. The temperature coefficient of the reference generator is calculated as 75C. A power management unit that involves a bandgap reference generator and a low dropout regulator is introduced and designed. Important performance parameters are extracted from the requirements of the capsule endoscopy transmitter. Hence, the layout area is designed to be small and output voltage variation is minimized over PVT corners. The layout of the system is designed and post-layout simulation results are reported in the study.
Bidirectional buck boost converter design

(Graduate School, 2024-08-09) Sarıgül, İlyas ; Çakır, Yüksel ; 504211211 ; Electronics Engineering

The importance of DC to DC converters increases with developing technology. Many of the electronic devices that we use contain AC/DC or DC to DC converters. One of the areas where DC to DC converters are most used is electric vehicles. DC to DC converters are used to charge the battery and energize the electric motors with the charged battery. There are many different types of DC to DC converters. Some of these have an isolated structure, while some have a non-isolated structure. The isolation status of the converter is determined according to the design needs. Converters operating as standard make a one-way conversion from the input direction to the output direction. However, due to the change and increase in today's needs, one-way DC to DC converters have become ineffective. Where bi-directional operation is required, two DC to DC converters had to be designed. This made the design both larger and less efficient. Therefore, using standard DC to DC converters bidirectionally by making some additions and arrangements is one of the most effective ways. Bi-directional operation is possible in both isolated and non-isolated DC to DC converter structures. Bi-directional buck boost converter can produce a regulated voltage both from input to output and from output to input. In this study, the details of the non-isolated structure that can operate bi-directionally are included. The non-isolated bi-directional converter is in buck boost converter topology. It contains four switching components in this structure. It is possible to operate this structure bidirectionally with the 4 MOSFETs used. While it operates in buck mode, buck boost mode and boost mode in the forward direction, it can operate in buck mode, buck boost mode and boost mode in the reverse direction. The way to achieve these modes is to determine the forward and reverse operating characteristics. The conditions under which the structure operates in forward or reverse direction depend on the input and output voltages. If appropriate source voltage is applied to the input of DC to DC, the structure works in the forward direction and produces output voltage. If the input and output voltage are not within an appropriate range, DC to DC converter goes into protection mode and produces no output. If the appropriate source voltage is applied to the DC to DC converter's output, the output side acts as an input and the input side acts as the output. It is possible to get voltage from the input side with the voltage applied from the output side. The bi-directional buck boost converter structure basically includes the following circuits: bi-directional current measurement circuits, voltage divider circuit MOSFET driver circuits, MOSFETs, switching inductor, microcontroller, auxiliary circuits and temperature measurement circuits. Management of operations within the converter is provided by the microprocessor. The microprocessor performs the operations of measuring input/output voltages, measuring bi-directional input/output currents, measuring temperature from the temperature sensor, and driving MOSFETs according to a certain algorithm. The operating mode of the converter is determined by the voltage and current measurement circuits in the structure. For forward operation, if the input voltage is greater than the output voltage, the converter operates in buck mode, if the input voltage is close to the output voltage, it operates in buck boost mode, and if the input voltage is lower than the output voltage, it operates in boost mode. In reverse operation, if the output voltage is greater than the input voltage, the converter operates in buck mode, if the output voltage is close to the input voltage, it operates in buck boost mode, and if the output voltage is lower than the input voltage, it operates in boost mode. Signals of certain pulse widths are applied to MOSFETs to produce input or output voltages. The width of these signals is determined by the voltage values the microcontroller measure from the input and output. This measurement takes place continuously. To obtain a constant output voltage in a structure where the input voltage varies, the pulse width must be constantly adjusted. The same is necessary for obtaining constant input voltage. As the current measurement circuits included in the converter design, both bi-directional current reading and limiting can be provided. The current can be read from both the input and output sides. If more current is drawn from the input or output of the DC to DC converter than the specified current limit, the current is limited. This limiting process is possible by adjusting the pulse width of the signal applied to the MOSFETs, just like adjusting the voltage.
Bir motor kontrol sisteminin model tabanlı donanım ve yazılım ortak tasarımı

(Lisansüstü Eğitim Enstitüsü, 2023-01-19) İn, Sedat ; Yalçın Örs, Sıddıka Berna ; Tiryaki, Hasan ; 504181281 ; Elektronik Mühendisliği

Günümüz teknolojisinde elektrikli motor ve motor sürücüler önemi büyük teknolojik cihazlardır. Elektrik enerjisini mekanik enerjiye aktaran bu cihazlar, endüstri ve bir çok otomasyon sisteminde kullanılmaktadır. Yaygınlaşan elektrikli araç teknolojisinde de farklı tipte birçok elektrik motoru ve motor sürücüsü kullanıma denk gelinebilir. Elektrikli motorlar ihtiyaç tipine ve kullanım alanına göre farklı tip ve farklı modellerde oluşturulabilir. Elektrik motorları yapıları ve çalışma ihtiyaçlarına göre 2 ana başlık altında ayrılmıştır. Bunlar doğru akım motorları ve asenkron elektrik motorlarıdır. Doğru akım motorları da kendi içlerinde 2 ana başlık altında incelenebilir. Doğru akım motor tiplerinden biri fırçasız doğru akım motoru iken, bir diğeri ise fırçalı doğru akım motorlarıdır. Her iki motor tipi için de farklı kontrol yöntemleri mevcuttur. Bu tez çalışmasında bir fırçasız doğru akım motoru için, motorun kontrolünü sağlayacak olan bir motor sürücüsünün donanım ve yazılım tasarımı çalışmaları yapılmıştır. Motor sürücü, elektrikli motoru istenen hız veya akım değerinde çalıştırmak için kullanılan bir cihazdır. Fırçasız doğru akım motorları yapıları gereği motor sürücüye ihtiyaç duymaktadır. Motor sürücünün model tabanlı tasarımı için ilk olarak motorun modelinin oluşturulması gerekir. Motora ait modelleme çalışmaları gerçekleştirilirken motor parametrelerinin doğru elde edilmesi önemli bir husustur. Motora ait modelleme parametreleri doğru elde edilmez ise tasarım hatalı oluşacaktır. Bu motor kontrol çalışmasında, motor kullanıcı tarafından sağlanan hız girdisi ile kontrol edilmiştir. Kontrol edilecek olan elektrikli motorun matematiksel modeli oluşturulmuş ve çeşitli kontrol algoritmaları ile test çalışmaları yapılmıştır. Test çalışmaları ile birlikte motor kontrolü için donanım yapıları oluşturulmuş ve model tabanlı tasarım yapılmıştır. Model tabanlı tasarım otomatik olarak yazılıma aktarılmış ve yazılım el ile kodlama yapılmadan tamamıyla model tabanlı olarak otomatik gerçekleştirilmiştir. Otomatik kod oluşturma için literatür de bulunan çalışmalar incelenmiş ve birçok farklı yöntem ile otomatik kod çalışması yapıldığı görülmüştür. Model tabanlı tasarım için MATLAB/Simulink ortamı kullanılmıştır. MATLAB/Simulink ortamında model tabanlı kod üretimi yapılabilen bir çok eklenti mevcuttur. Farklı işlemci, Digital Signal Processor (DSP) veya Field Programmable Gate Array (FPGA) tipleri için otomatik kod oluşturma çalışmaları mevcuttur. Bu çalışmada işlemci için tasarım yapılacağından işlemciler için otomatik kod üretimi yapılan çalışmalar incelenmiştir. İşlemciler için geliştirilen birçok farklı kod üretim yöntemi mevcuttur. Yapılan bu çalışma da STMicrocontroller ailesine ait bir işlemci kullanılacağından STMicrocontroller ailesi için kod üretimi yapan yapılar üzerinde durulmuştur. STMicrocontroller ailesine ait olan STM32 işlemciler için otomatik kod oluşturma imkanı tanıyan Waijung Blockset ve STM32-MAT Target blok setleri bu tez çalışmasında detaylıca anlatılmıştır. Her iki otomatik kod oluşturma çalışmasının da Simulink ortamında nasıl kullanılacağı ve kurulumunun nasıl yapılacağından bahsedilmiştir. Motor sürücü tasarımı MATLAB/Simulink ortamında gerçekleştirilmiştir. Tasarım için ihtiyaç duyulan bloklar parça parça oluşturulmuş ve MATLAB/Simulink ortamında simüle edilmiştir. Tasarım oluşturulurken, kullanılacak olan motor tipi kadar motorun ihtiyaç duyacağı yükün ve karşılamasını beklediğimiz gerekliliklerin ne olduğunu bilmek de önemlidir. Bu nedenle, motorun kullanılacağı alan olan araç içerisinde motorun nasıl bir yükü karşılaması gerektiği hesaplanmıştır. Araca ait sürtünme katsayısı, eğim, ön yüzey alanı ve ortama ait hava direncine kadar bir çok parametre ile karşılanması gereken yük elde edilmiştir. Motor modeli Simulink ortamında oluşturulmuş ve simulasyon çıktıları izlenerek yazılım modellemesi yapılmıştır. Yazılım modellemesi oluşturulurken kullanılacak olan işlemci tipine uygun tasarım yapılmıştır. İşlemci tipine özgü tasarım ile model direkt olarak yazılıma aktarılabilmiştir. Kullanılan işlemci modeli STMicrocontroller ailesine ait olan bir işlemcidir. Bu nedenle oluşturulan tasarım, Waijung Blockset veya STM32-MAT Target yapıları kullanılarak işlemciye aktarılmalıdır. Bu çalışmada otomatik koda dönüştürme işlemi için STM32-MAT Target yönteminin kullanılmasına karar verilmiştir. İşlemci STM32-MAT Target ile koda dönüştürüleceği için, işlemciye ait konfigürasyon çalışmaları STM32CubeMX arayüzü ile gerçekleştirilmişir. STMCubeMX arayüzü ile konfigürasyonun oluşturulması için gerekli olan işlemci seçimi ve seçilen işlemciye ait ADC, TIMER, Haberleşme hatları ve diğer çevre birimlerin nasıl konfigüre edileceği detaylıca anlatılmıştır. Otomatik kod oluşturmak için kullanılan Waijung Blockset ve STM32-MAT Target bloklarının kurulumları nasıl yapıldığı detaylıca gösterilmiştir. Her iki yöntem içinde birer örnek sunulmuş böylelikle koda dönüştürme ve uygulama örneklendirilmiştir. Motor sürücü tasarımı oluşturulurken istenen hız değerine uygun çıktılar verecek şekilde bir kontrol sinyali üretilmesi gerekmektedir. Motor sürücüler farklı bir çok yöntem ile kontrol edilebilmektedir. Motor kontrolü için, Bulanık PID kontrolcüler, Model Predictive Control (MPC) ve geleneksel PID kontrolcüler gibi seçeneklere literatürde rastlamak mümkündür. En yaygın kontrolcü tipi ise Proportional-Integral-Derivative (PID) kontrolcüdür. Motor Yazılım modellemesi yapılırken, motorun PID kontrolcü ile kontrol edilmesine karar verilmiştir. Geleneksel PID yöntemleri, uygulamanın gerçekleştirildiği motor modeli için istenen çıkış değerlerini tam olarak sağlayamamaktadır. Ek olarak geleneksel PID kontrolcülerin oluşturduğu katsayılar kontrol edilmek istenen fırçasız doğru akım motoru için uygulanabilir olmalıdır. Bu çalışmada geleneksel PID ile kontrol sistemi üretilmeye çalışılmıştır. Kontrol katsayıları belirlenirken Ziegler-Nichols açık çevrim cevabı ve Ziegler-Nichols kapalı çevrim cevabı kullanılmıştır. Ziegler-Nichols yöntemleri ile kontrolcü katsayıları elde edilmiştir. Elde edilen bu katsayılar ile kontrol işareti üretilmiştir. Üretilen kontrol işaretinin, güç için kullanılan sistemin gerilim değerini aştığı ve gerilim hattı üzerinde sürekli osilasyona sebep olduğu görülmüştür. Sistemin batarya enerjisi ile besleneceği düşünüldüğünde bu durum sistemin uygulanabilirliğini kaybetmesine neden olur. Geleneksel PID yerine farklı çalışmalar incelenmiş ve PID içerisinde kullanılan kontrol katsayıları Linear-Quadratic-Regulation (LQR) yöntemi ile elde edilmiştir. LQR yöntemi ile sistem girdisinin hassasiyeti ayarlanabilmektedir. Böylelikle uygulanabilir gerilim seviyesinde kontrol işareti üretmek mümkün olur. LQR yöntemi ile elde edilen PID kontrolcüsünün katsayıları motoru istenen hız değerine ulaştıran en doğru kontrol işaretini üretmiştir. Üretilen kontrol işareti sistem osilasyonunu yok denecek kadar düşürmüştür. Ziegler-Nichols yöntemleri ile elde edilen katsayılar ve LQR yöntemi ile elde edilen katsayılar karşılaştırılmıştır. Yapılan karşılaştırma sonucunda motor sürücü kontrol işareti LQR yöntemi ile hesaplanan PID katsayıları aracılığıyla oluşturulmuştur. Motor sürücü donanım yapısı 4 farklı kart ile gerçekleştirilmiştir. Böylelikle sürücü yapısının modüler olması hedeflenmiştir. Olası aşırı yüklenme vb. durumlarda zarar gören elektronik kartı değiştirmek mümkündür. Motor sürücü yapısı için oluşturulan elektronik kartların üç tanesi motor sürücü sisteminde bir tanesi ise motor içerisinde olacak şekilde tasarlanmıştır. Motor sürücü içerisinde bulunan üç kart, Regüle kartı, Kontrol kartı ve Güç kartıdır. Bu kartlar aracılığıyla motor sürücüye ait PCB tasarımları işlevlerine göre ayrılmıştır. Kontrol kartı motor sürücüsünün beyni olarak işlev yapmaktadır. Tüm kontrol algoritması bu kartta bulunan işlemci ile gerçekleştirilir. Kart tasarımı yapılırken ihiyaç duyulacak bütün çevre birimler kart tasarımına eklenmiştir. Bu çevre birimler haberleşme, filtreleme ve sinyal işleme gibi çevre birimlerdir. Kart içerisindeki tüm çevre birimlerin şematik tasarımları paylaşılmıştır. Şematikler oluşturulurken nelere dikkat edildiği ve nasıl oluşturulduğu detaylı bir şekilde anlatılmıştır. Şematik sonrası oluşturulan PCB çizimleri gösterilmiştir. Çevre birimlerin PCB üzerinde konumlandırılırken dikkat edilen parametreleri açıklanmıştır. Kullanılan çevre birimlerin neden kullanıldığı bahsedilmiştir. Kontrol kartı çevre birimler ile çevre birimleri besleyen güç hattını da içerisinde barındırmaktadır. Tüm çevre birimler farklı enerji seviyesinde besleme ihtiyacı duyabilir. Kontrol kartı tüm bu enerji ihtiyaçlarını karşılamak üzere karta harici olarak gelecek olan bir besleme gerilimine ihtiyaç duyar. Kontrol kartının ihtiyaç duyduğu besleme 12V seviyesindedir. İşlemci ve çevre birimler için ihtiyaç duyulan gerilim seviyeleri kontrol kartı içerisinde dönüştürülür. Böylelikle, Tüm çevre birimlerin beslemesi gerçekleştirilir. Regüle kartı ile hem kontrol kartının hem de güç kartının ihtiyaç duyduğu 12V besleme gerilimi motor beslemesinden elde edilir. Regüle kartı enerji girişini sistem dışından, batarya üzerinden elde edecektir. Gelen enerji girişi manyetik bozulmalara maruz kalabileceğinden, regüle kartı tasarımı bu öngörüler doğrultusunda filtreleme ile gerçekleştirilmiştir. Güç kartı, Kontrol kartından gelen komutları gerçekleştiren, içerisinde MOSFET'lerin ve kapı sürücülerin bulunduğu donanımsal birimdir. Kontrol kartı ile oluşturulan tetikleme darbeleri güç kartına aktarılır. Kontrol kartından gelen sinyal ile Güç kartında bulunan kapı sürücülerin faz tetiklemeleri gerçekleştirilir. Güç kartı içerisinde 18 adet MOSFET bulunmaktadır. Üç fazdan oluşan motor için motor sürücüde minimum 6 adet anahtarlama elemanı kullanılması gerekir. Güç kartı yapısında 18 adet MOSFET kullanımı ile oluşacak akım yoğunluğu 3 farklı anahtarlama elemanı üzerinden aktarılmıştır. Her bir fazın hem yüksek değerlikli anahtarlama elemanı hem de düşük değerlikli anahtarlama elemanı için 3 adet MOSFET kullanılmıştır. Güç kartı içerisinde motora ait enerji akışının gerçekleştirildiği iletim hattını barındırmaz. Enerji akışının gerçekleşmesi baralar aracılığıyla sağlanmıştır. Güç kartı baralara montajlı MOSFET'lerin tetiklemesini sağlamaktadır. Bu üç motor sürücü kartı dışında bir PCB'de motor içerisinde motorun pozisyon bilgilerinin alındığı Hall Sensör kartıdır. Hall sensör kartı ile alınan bilgiler işlemciye kablo aracılığıyla aktarılır. işlemci içerisinde işlenen pozisyon bilgileri gerekli komütasyon adımlarını üretir. Böylelikle motorun dönüşü için gerekli sinyaller elde edilmiş olur. Tez çalışması ile hedeflenen tasarım bu doğrultuda gerçekleştirilmiştir.
Characterization and modeling of negative-biastemperature instability in 40 NM CMOS technologythrough long short-term memory (LSTM) networks

(Graduate School, 2023-02-02) Gencer, Fikret Başar ; Yelten, Mustafa Berke ; 504191255 ; Electronics Engineering

In this thesis, the time-based degradation effect of the negative-bias temperature instability (NBTI) phenomenon, which is one of the aging mechanisms in transistors, is investigated. This type of aging effect is seen in two separate phases of the stress and recovery process. The time-series nature of the problem suggests using a model capable of predicting temporal changes. Thus, long short-term memory (LSTM) networks have been used to model NBTI aging effect. Negative-bias temperature instability is essentially an aging effect specific to p-type transistors. More generally, bias temperature instability occurs in both p-type and n-type metal-oxide-semiconductor field-effect-transistor (MOSFETs). It is also seen as positive-bias temperature instability in n-type transistors, yet its effect is more prominent in p-type transistors. This mechanism is seen when p-type transistors operate at high temperatures and are exposed to high negative gate voltages. Manufacturing defects, trapping of positively charged holes in the dielectric region, and the formation of interface states due to negative voltage can be shown as the main reasons for NBTI. The result could bring side effects such as a decrease in the transistor drain current and an increase in the threshold voltage. In deep learning, artificial neural networks can be used for transistor modeling because data-driven modeling can be presented instead of revealing a physical model based on the transistor characteristic equations. In order to model aging effects with deep learning methods, stress periods should not be ignored, which is directly related to the temporal nature of aging. Since the measurements taken at certain time intervals in the observation of the NBTI effect are related to each other, the artificial neural network algorithm should be suitable for this. For this reason, long-short-term memory networks have been used in this study which is under the category of recurrent neural networks (RNN), and have been developed as a solution to the vanishing gradient problem experienced by networks developed with RNN during learning processes. LSTM networks change the unit cell structure by introducing a long-term memory mechanism to RNN networks, and thus, they do not encounter the problem of vanishing gradient, which occurs when the effects of the information that needs to be remembered in the long-term may arise during the training process. In addition, it is mainly used in studies such as taking time series inputs while training for pattern recognition and prediction. The working mechanism of LSTM is suitable since the NBTI problem can actually be transformed into a time series problem. In this thesis, an automated setup and special test chips developed within the scope of the TÜBİTAK project were used for NBTI characterization and modeling. Thanks to these developed chips and the circuit board, the chips can be exposed to appropriate stress conditions. In these specially designed structures, there are 64 separate transistors, 32 of which are RF and 32 of which are normal MOSFETs. Half of these 32 transistors are allocated as n-type transistors, and the remaining half as p-type transistors with different transistor sizes. The test chip structure contains a decoder in the input layer and sends the desired input address to the 32 multiplexers, which can turn all of the transistors on and off in response to the signals applied to their inputs, as well as open or close the 32 switch structures. These switch structures control these 32 transistors whose drain, source, and gate terminals are connected in parallel to the chip output, can be biased externally, and the current value can be measured. The test setup contains different industrial measuring instruments and enables them to be controlled with a computer program developed in the LabVIEW environment. After the appropriate measurement standards are determined in the LabVIEW environment, the desired inputs, such as the measurement time, how many measurements will be taken, and which transistors will be measured, are determined. Afterward, measurements are started from the transistors left to the stress environment to be applied, depending on the situation. In the measurements, 4 different p-type transistors in the test chip were used. The measurements were collected by changing both the drain-source voltage and the gate-source voltage in the form of the current-voltage relationship. These measurements were first made under room conditions. Afterward, only the environment temperature was increased. After that, it is aimed to observe the NBTI effect with the negative gate voltage while keeping the temperature at a high level. The transistors were exposed to the negative voltage at certain intervals, and then they were expected to enter a temporary recovery period for a certain period of time. This step was repeated 5 times with different stress and different temporary recovery measurements. On the last stress measurement, temporary recovery was not waited to end, and measurements were taken at regular intervals. In this way, a total of 18 sequence characteristic measurements, 50 points per measurement, with 13 different recovery measurements in 5 different stress processes, were recorded in the dataset with the aforementioned methods. As a result of the collection and detailed analysis of the mentioned measurements, the data were first separated into appropriate sequences in order to create the appropriate model. In order to use a network structure such as LSTM, data can be given as two different types of input. The first of these is to think of the data as a time series problem and to express the appropriate parameters with overlapping and sliding windows in the input space, and the other is to consider each of the data in the dataset as data taken at a separate time and apply them one by one in sequences. Since both methods have their own contributions to the training of the model, two different decomposition methods were used. Firstly, in order to make a model that predicts the current with the high success of the sliding windows method, the past values of the current and the parameters such as terminal voltages at these values, stress voltage, and stress duration are included in the inputs, and the drain current value after a certain step is tried to be estimated. In the other method mentioned, the transistor current data is used only in the output space, and the features that allow obtaining that output are used in the input space. With these inputs, the model was trained with monitoring machine learning error techniques. such as root mean square error. In conclusion, the collected dataset and the modeling have been demonstrated as LSTM structures that are successful in modeling aging effects, such as NBTI. Thanks to the developed model, the stress times that are unseen to the model were estimated, and these were observed as expected when compared to the previous data. In addition, optimizing the recovery process becomes a short-term problem because it is possible to discover exactly when the recovery will occur thanks to the model. With these achievements, it can be revealed how the transistors developed by the manufacturers can respond to different situations with such a model. Another output is that the model can be used in different areas by developing designs that are NBTI-aware and taking precautions accordingly by transferring the developed model to a circuit simulation program.
Classification of chest X-rays by divergence-based convolutional neural network

(Graduate School, 2022) Kılıç, Muhammed Nur Talha ; Ölmez, Tamer ; 731698 ; Electronics Engineering Programme

The importance of imaging methods in the field of health is increasing day by day with the opportunities provided by technology. Imaging without physical intervention is both more convenient and less costly for the patient and one of the ways to diagnose faster. Diagnosis of diseases and taking action, especially in the early stages of epidemic diseases, are among the most effective methods in the fight against these diseases. Correct treatments are applied against diseases that can be differentiated from each other, thus the patient's recovery is ensured. Chest radiographs are also one of the most frequently used methods in the field of imaging, and the damage caused by various viruses or bacteria to the lung can be understood and diagnosed with X-ray images. At the same time, it ensures that health systems continue with minimum damage by providing the necessary data for health workers to take precautions in case of an infectious side of the disease. Covid-19, which entered our lives towards the end of 2019 and caused the death of millions of people in more than 2 years, directly damages the lungs and causes the lungs to not perform their functions. Problems that occur in the lungs by reducing oxygen saturation cause many issues, especially respiratory problems in patients. Some of the problems seen in patients with suspected Covid-19 occur in the lungs and these changes caused by the disease can be detected by X-rays. However, it is not known to what extent the effects of viruses such as Covid-19, which have been in existence for years but have the capacity to infect people in the near future, and it is not possible to deliver treatment techniques to all parts of the world in a short time. In other words, it is a very long and laborious process to be able to effectively diagnose diseases that we can call new diseases that come into our lives by health workers around the world. For this reason, engineering applications in the field of medical imaging are promising in many respects. For example, AI-assisted engineering applications, which have become very common recently, bring many advantages. These achievements can be listed as follows: •Detailed analysis opportunity •Instant access to developments in the world •Ability to be easily updated •Possibility to get results with high accuracy and fast •To alleviate the burden of healthcare workers •Cost-reducing contributions with fewer employees •Reaching areas with low or limited access to the health system •Reducing the contagious risk of the disease by reducing direct or indirect contact with patients •Creating systems whose accuracy and reliability are increasing day by day with continuously trained models. •Opportunity to create models trained with more examples than specialist doctors can see throughout their career Although the developments mentioned are undeniably positive, the physical hardware needs that come with artificial intelligence supported applications should not be ignored.
Communication range extending PSK backscatter modulation in passive RFID

(Graduate School, 2024-02-05) Evecan, Kazım ; Özoğuz, İsmail Serdar ; 504051231 ; Electronics Engineering

In this study, analyses and simulations to increase the communication distance of passive RFID systems in forward and reverse directions have been carried out through equations. All modulation techniques have been compared fairly with the equations obtained by classical circuit theory and based on the power of the RFID tag and reader. It has been shown that the time at which the average peak power consumption of the tag occurs during communication affects the communication distances. After using the parameters determined by the regulatory institutions and obtained from the literature, the free parameters on the system were obtained by keeping any parameter constant, and thus concrete data was obtained. The results were further confirmed using data from recent studies found in the literature with tag threshold power between 664 nW and 1 μW. It was concluded that the performance of binary phase shift keying modulation is better than amplitude shift modulation in terms of communication distance, signal-to-noise ratio or bit error rate, and receiving antenna gain. Long communication distance is important in environments where there are many obstacles and noise, as it enables the tag to work successfully. The long communication distance feature can be transformed into a receiving antenna that can be used in smaller sizes and at less cost. Similarly, it also provides more reliable communication with a higher signal to noise ratio or less bit error rate at the receiving end. It has now been observed that the communication distance of RFID systems has begun to be limited by backward communication rather than forward communication, which provides energy and information. This situation shows that it will be necessary to switch to a bistatic antenna configuration for the reader instead of a monostatic antenna configuration. Equations have been put forward that the reader configuration change is mandatory for the given parameters after the power of the tag exceeds a threshold level. It has been concretely demonstrated by equations that phase shift modulation has the potential to increase speed. This potential can be implemented without changes from the EPC Class I Gen II rules and generally without changes in communication distance. Depending on the time at which the average peak power consumption on the tag occurs during communication, increasing the speed may require sacrificing some communication distance. Phase shift keying modulator varactor size reduction opportunity has been shown by equations to shrink die area. Depending on peak power consumption during communication, it can be exploited completely or partially.
Deep learning based fruit and vegetable recognition for android pos devices

(Graduate School, 2022-01-17) Ekici, Ege ; Güneş, Ece Olcay ; 504181209 ; Electronics Engineering

With the recent improvements in technology, time and expense-saving products have gained an important trend in marketplaces. Recent increases in shopping trends created a need for faster payment technologies. Even though the barcode system is currently one of the most popular technologies being used, this system is not fault-tolerant and likely to be inefficient for unpackaged products by being human dependent. As an example, fruits and vegetables are two of the most popular unpackaged product categories that are being priced based on the amount bought and cashiers usually enter a product code manually in case of purchase. Along with that, some businesses have installed self-checkout tables where customers can handle their own payments to decrease shopping time in rush hours and save on employee expenses. But self-checkout tables depend on customer trust when it comes to unpackaged products since any customer can select a product of a different price from the list. At the same time, self-checkout tables are very costly for most businesses. As a solution to the aforementioned problems, a system is proposed in this project that aims to benefit in security, expense, and time. The system aims to be advantageous by not creating an additional hardware expense by using the Point of Sale (POS) devices that most businesses already have. Focusing on fruits and vegetables, a recognition system is added using the device camera to prevent human-dependent security problems of the existing systems. Various techniques are experimented with to achieve a real-time system. In this project, a dataset consisting of 14 types of packaged and unpackaged fruits and vegetables is used. Related works usually implemented object classification and object recognition algorithms for similar problems but since objects can exist in different locations and amounts on a frame, an object recognition algorithm is decided to be more suitable for this project. Along with object detection algorithms being more complex than object classification algorithms, having POS devices with limited resources created a risk of the device being insufficient against the high computational needs of the system. For this reason, decreasing the model size and making the model closer to real time by decreasing the computation time became one of the purposes of this project. Therefore, among the object detector methods, it is decided to select a one-shot detector model. "You Only Look Once (YOLO)" is one of the state-of-the-art one-shot algorithms and is a well-known algorithm that has several versions developed over years. In this project, two of the latest versions; YOLOv4 and YOLOv5 are used and compared under several performance metrics and the best results are obtained with YOLOv5 with a mAP score of 98%. Later, several quantization methods are examined and compared for the purpose of creating a model of smaller model size and better performance. Among the quantization methods, best results are achieved with Full Integer Quantization, and model size is decreased by 75%. The proposed detection model is deployed on an android-based 400TR POS device developed by Token Financial Technologies with MT8167A (1.5 GHz) CPU. On the final system, inference time is observed as 1.332 seconds.
Derin obje sezicilerle tümleştirilmiş bayesçi filtreleme ile videoda obje izleme

(Lisansüstü Eğitim Enstitüsü, 2021) Gürkan Gölcük, Filiz ; Günsel Kalyoncu, Bilge ; 691735 ; Elektronik ve Haberleşme Mühendisliği

Güvenlik, hareket ve aktivite tanıma, robotik uygulamaları ve daha birçok uygulamada gerek duyulan obje izleme, belirlenen bir veya daha fazla hedef objenin konumunun video boyunca kestirilmesi olarak tanımlanır. Uzun yıllardır bu alanda yapılan çalışmalar, izleme başarımını arttırmanın yanı sıra, örtüşme, deformasyon, ölçek ve görünüm değişimi gibi izlemeyi zorlaştırıcı etkilere karşı gürbüz algoritmalar geliştirmeyi amaçlamaktadır. Tez çalışması kapsamında, üretici ve ayırıcı yöntemlerin entegre edilmesine olanak sağlayan obje-sezme-ile-obje-izleme (tracking-by- detection - TBD) yaklaşımı altında, IDPF-RP, L1DPF-M ve TDIOT olarak adlandırılan, üç farklı obje izleyici önerilmiştir. Önerilen tüm izleyicilerde, tek obje izleme problemi üzerinde yoğunlaşılmakta ve objenin son konumu, Bayesci filtreleme tabanlı bir obje izleyici bir derin obje sezici ile tümleştirilerek kestirilmektedir. Derin obje sezici olarak yüksek lokalizayon doğruluğuna sahip Mask R-CNN sezici kullanılırken, Bayesçi filtrelemede hedef obje modellemede başarılı olduğu gösterilen renk-tabanlı parçacık filtreleme ve seyrek parçacık filtreleme kullanılmaktadır. İzleyicilerin bir diğer ortak noktası, kullanılan derin obje sezicinin izleme amacıyla yeniden eğitilmesini, ya da izleyicinin uçtan-uca yeniden eğitimini gerektirmemeleridir. Böylelikle etiketlenmiş izleme verisi olmaması durumunda çalışabilen, çevrim dışı eğitim yükünü en aza indiren, çok farklı derin obje sezicilerin farklı omurga mimarileri ile tümleştirilebilmesine olanak sağlayan obje izleyicilerin gerçeklenmesi hedeflenmiştir. IDPF-RP (Interleaving deep learning and particle filtering by region proposal suppression), VRCPF obje izleyici ile senkronize çalışan Mask R-CNN obje sezici kararlarını tümleştiren yeni bir karar tümleştirme mekanizması sunmakta, bu sayede objenin son konumu, izleyici ve sezici arasındaki karar birliğini enbüyükleyecek şekilde belirlenmektedir. IDPF-RP lokalizasyon hizalama katmanı (LH), Mask R-CNN sezicinin ölçek değişimlerine uyumluluk ve lokalizasyon doğruluğu avantajı ile VRCPF izleyicinin hedefe lokalize olma özelliğinden yararlanan bir tümleştirme gerçekler. Bu sayede izleme performansını doğrudan etkileyen aday obje BB'lerinin, içeriğe bağlı olarak değişen sayıda ve yüksek lokalizasyon doğruluğu ile örneklenmesi sağlanabilmekte, böylelikle izleme sürekliliği arttırılmaktadır. IDPF-RP, derin obje seziciden alınan geri besleme ile, hedef obje modelini güncelleyerek ölçek, ışıklılık ve görünüm değişimleri gibi obje izlemeyi zorlaştıran problemlere karşı gürbüzlüğü arttırmaktadır. Tez kapsamında önerilen bir diğer obje izleyici, L1DPF-M, Mask R-CNN derin obje sezici ve seyrek parçacık filtresini TBD yaklaşımı altında entegre eden yeni bir model sunmaktadır. Hedef obje modellemede kullanılan seyrek gösterim, derin obje sezicinin kılavuzluğunda güncellenerek, örtüşme, bakış-açısı değişimi gibi etmenlerden kaynaklanan obje görünüm değişikliklerine karşı gürbüzlük arttırılmaktadır. L1DPF-M, önerilen yeni PF gözlem modeli sayesinde, sezici ve izleyici arasında fikir birliğini ön plana çıkararak hedef objenin son konumunun daha doğru kestirilmesine olanak tanımaktadır. Bunun yanı sıra, L1DPF-M kapsamında önerilen yeni durum vektörü ile, obje hareketinin öteleme, dönme, ölçekleme ve kırpma olarak farklı komponentlerle modellenebilmesi bu sayede obje sınırlarının deforme BB'ler ile izlenebilmesi ve lokalizasyon doğruluğunun arttırılması sağlanmıştır. L1DPF-M, Mask R-CNN çıkışında elde edilen ve objeye piksel bazında erişim sağlayan bölütleme maskelerini kullanarak, izlemenin afin dönüşümlere gürbüzlüğünü arttırmaktadır. Tez kapsamında geliştirilen üçüncü obje izleyici, TDIOT, videodaki zamansal bilginin 3B CNN, LSTM ve benzeri mimariler kullanılmaksızın, işlem yükü çok arttırılmadan modele katılmasını amaçlamaktadır. IDPF-RP ve L1DPF-M den farklı olarak mimarisinde yalnızca PF izleyicinin parçacık örnekleme modülünü içerir ve hedefin son konumunun kestiriminde derin obje seziciye öncelik verir. Literatürdeki birçok derin izleyiciden farklı olarak, sezici eğitiminde kullanılan mimarinin izleme amacıyla transfer öğrenme ile yeniden eğitilmesini, ya da uçtan-uca yeniden eğitimini gerektirmez. Önerilen çıkarım mimarisinde Mask R-CNN aday bölge öneri katmanına eklenen parçacık örnekleyici, objenin geçmiş çerçevelerdeki konum bilgisini kullanarak, objeye uyumlu ölçek ve boyutlarda aday obje bölgelerinin önerilmesine olanak vermektedir. Öte yandan tepe katmanına eklenen "Benzerlik Eşleme" ve "Yerel Arama ve Eşleme" katmanları ile siyam benzerlik kriterine dayalı veri ilişkilendirme gerçeklenir. TDIOT obje izleyicinin obje giriş çıkışlarının da olduğu uzun süreli izleme isterlerini karşılaması amacıyla, yerel ikili örüntü tabanlı bir hedef-obje-doğrulama katmanı izleme mimarisine eklenmiş, uzun süreli izleme başarımının arttırıldığı gösterilmiştir. TDIOT doğrulama katmanının, insan, araba ve benzeri belirli objeler için eğitilmiş yeniden yakalama ağları ile değiştirilmesiyle, daha yüksek işlemsel karmaşıklığa karşın, obje doğrulama başarımının arttırılması olanaklıdır. Önerilen yöntemlerin başarımı literatürde sıklıkla kullanılan VOT ve VOT-LT veri tabanlarına ait videolar üzerinde raporlanmaktadır. Her üç yöntem için güncel izleyiciler ile karşılaştırmalı olarak sunulan izleme performansları, önerilen izleyicilerin lokalizasyon doğruluğunu önemli ölçüde arttırdığını göstermektedir. VOT2016 veri setine ait videolarda yapılan performans raporlamaları, IDPF-RP ve L1DPF-M ile güncel izleyicilere kıyasla sırasıyla \%7 ve \%6 daha yüksek başarım oranına (IoU-th=0.5) ulaşıldığını göstermektedir. Ayrıca, TDIOT ile lokalizasyon doğruluğunun (accuracy), VOT2016'nın en yüksek başarımlı izleyicisine göre \%3 oranında arttırıldığı, TDIOT-LT ile uzun süreli videolarda, literatür ile karşılaştırılabilir izleme performansına ulaşıldığı raporlanmaktadır. Bunun yanı sıra, izleme performansı her bir zorluk kategorisi için ayrı olarak analiz edilmiş ve önerilen izleyicilerin birçok zorluk durumunda izleme performansını arttırdığı gösterilmiştir. VOT2018 veri setine ait videolarda yapılan testler, IDPF-RP izleyicinin, ölçek değişimi içeren videolarda başarım oranını \%4, L1DPF-M izleyicinin, ışıklılık değişimi içeren videolarda başarım oranını \%5 oranında arttırdığını göstermektedir (IoU-th=0.5). Öte yandan, TDIOT obje izleyici, özellikle ışıklılık ve ölçek değişimine karşı gürbüzlüğü arttırarak, izleme doğruluğunu sırasıyla \%4 ve \%2 oranında iyileştirmektedir. TDIOT-LT ise bakış açısı değişiminin olduğu uzun süreli videolarda en yüksek izleme başarımına ulaşmaktadır.
Derin öğrenme ağları kullanılarak doğal ortamda hastalıklı domateslerin belirlenmesi

(Lisansüstü Eğitim Enstitüsü, 2022-06-28) Kapucuoğlu, Köksal ; Kırcı, Mürvet ; 504181277 ; Elektronik Mühendisliği

Birleşmiş Milletler ile Gıda ve Tarım Örgütünün yayımlandığı raporlara göre, 2050 yılında dünya nüfusunun 7 milyardan 10 milyara çıkması beklenmektedir. Bu kurumların yayımladığı diğer bir raporda, 2050 yılında beklenen nüfusu beslemek için önümüzdeki yıllarda dünya genelindeki gıda üretiminin %70 oranında artması beklenmektedir. Kentleşmeden dolayı tarımdaki iş gücünün azalmasından ve geçmişten günümüze kadar gelen geleneksel yöntemlerle gıda üretimin bu kadar arttırılması mümkün olmayacağından tarımda teknolojiden faydalanmak gerekmektedir. Bu anlamda tarım, teknolojik gelişmelerden pozitif anlamda etkilenen en önemli sektördür. Tarımda teknolojik anlamda son dönüşümünü temsil eden tarım 4.0 ile birlikte akıllı tarım ve dijital tarım konuları popüler hale gelmiştir. Akıllı tarımla birlikte gelen otomasyon sistemlerinin en çok uygulandığı alanlardan biri de hasat otomasyonudur. Yetiştirme ve hasat dönemi arasındaki süreyi en verimli şekilde geçirmek, üretilen ürünün kalitesine ve hasat miktarına direkt etki etmektedir. Bu sebeple, yetiştirme ve hasat dönemi arasındaki sürede, hasta bitkilerin tespit edilmesi ve ilaçlanmasının en doğru şekilde yapılması gerekmektedir. Nüfusla birlikte gerekli olan gıda ihtiyacının sürekli arttığı bu ekosistemde, dünyada üretim-tüketim miktarı ve geniş kullanım alanları baz alındığında, domates, en önemli sebzelerin başında gelmektedir. Domates yetiştiriciliği sırasında, yüksek doğruluğa sahip bir hasat otomasyon sisteminden yararlanmak bir gereksinim haline gelmiştir. Geleneksek yöntemlerle domates yetiştiriciliğinde; verilecek gübre miktarı, ilaçlama zamanı ve hasta olan domateslerin tespiti, insana bağımlılığı açısından hataya ve verimsiz bir süreç yönetimine açıktır. Bu yüzden son yıllarda hasat otomasyon sistemlerinde, insan bağımlılığını en aza indiren ve karmaşık sistemlerde bile yüksek doğrulukta ve hızda sınıflandırma yapan derin öğrenme teknolojisinden yararlanılmaktadır. Bu alanda yapılan çalışmaların çoğunda, hazır ortamlarda çekilen domates görüntülerinden oluşan veri kümeleri kullanılmıştır. Bu yüzden yapılan çalışmalar sonucunda sunulan derin öğrenme ağlarından çoğu, saha ortamında çalışmaya uygun değildir. Bahsedilen bu sorunlara karşı bu çalışmada, doğal saha koşullarında da yüksek hızda ve doğrulukla sınıflandırma yapabilen bir sistem önerilmiştir. Son yıllarda yaygın bir şekilde kullanılan derin öğrenme ağları incelenerek performans metrikleri belirlenmiştir. Daha sonra farklı davranıştaki veri kümeleri ile eğitilerek, eğitilen modellerin performansları incelenmiştir. Bu çalışmada; AlexNet, SqueezeNet, MobileNet v1, MobileNet v2, ResNet-50, GoogleNet, Inception v3 ve Inception ResNet v2 ile birlikte toplam 8 farklı derin öğrenme ağı incelenmiştir. Veri kümesi olarak; sınıflandırma çalışmalarında yaygın bir şekilde kullanılan Plantvillage ve Tiny-imagenet veri kümesi ile birlikte bu çalışmada kullanılmak için oluşturulmuş olan Çanakkale domates tarlası veri kümesi kullanılmıştır. Plantvillage veri kümesinde, 9 hastalıklı domates yaprağı sınıfı ve 1 sağlıklı domates yaprağı sınıfı olmak üzere toplam 10 sınıf vardır. Tiny-imagenet veri kümesinde 200 farklı nesne sınıfı bulunmaktadır. Bu çalışmada kullanılması için, Çanakkale-Erenköy'de bir domates tarlasında doğal saha şartlarında çekilen domates görüntülerinden oluşan Çanakkale domates tarlası veri kümesi oluşturulmuştur. Çanakkale domates tarlası veri kümesi oluşturulurken, dahil edilen doğal etkenlere göre bu veri kümesi iki şekilde temsil edilmiştir; temel Çanakkale domates tarlası veri kümesi ve karmaşık Çanakkale domates tarlası veri kümesi. Temel Çanakkale domates tarlası veri kümesindeki her bir görüntü, çekim tekniklerinden ve doğal şartlardan kaynaklanan ışık farklılıkları, görüntü yakınlığı, blur çekim, görüntü çerçevesinde yaprakların olması gibi etkenler içermektedir. Karmaşık Çanakkale domates tarlası veri kümesindeki her bir görüntü ise, temel veri kümesindeki etkenlerin dışında dal, başka bir domates, yaprak gibi ekstra etkenler içermektedir. Bu çalışmada yapılan denemeler sonucunda, Tiny-imagenet veri kümesi ile derin öğrenme ağlarının eğitiminde en iyi sonuca, %42.62 doğrulama doğruluğu ile Inception v3 ağı ile ulaşılmıştır. Plantvillage veri kümesi ile derin öğrenme ağlarının eğitiminde en iyi sonuca, %99.1 ile MobileNet v1 ağı ile ulaşılmıştır. Temel Çanakkale domates tarlası veri kümesi ile derin öğrenme ağlarının eğitiminde en iyi sonuca, %99.78 doğrulama doğruluğu ile Inception ResNet v2 ağı ile ulaşılmıştır. Karmaşık Çanakkale domates tarlası veri kümesi ile derin öğrenme ağlarının eğitiminde en iyi sonuca, %92.92 ile GoogleNet ağı ile ulaşılmıştır. Ayrıca yapılan denemeler sonucunda derin öğrenme ağlarının performans metrikleri incelenmiştir. Bu incelemeye göre; AlexNet, ResNet-50, Inception v3 ve Inception ResNet v2 gibi derin öğrenme ağlarının eğitim maliyeti olarak yüksek eğitim süresine ve model boyutuna sahip olduğunu tespit edilmiştir. Özellikle veri boyutu büyüdükçe, eğitim süresinin de bire bir oranda arttığı belirlenmiştir. Yüksek eğitim maliyetine sahip derin öğrenme ağları arasından en iyi sonuç veren Inception v3 ağının eğitimi; Tiny-imagenet veri kümesi üzerinde 7.5 saat, Plantvillage veri kümesi üzerinde yaklaşık 4 saat, temel Çanakkale veri kümesi üzerinde 5 dakika ve karmaşık Çanakkale veri kümesinde ise 20 dakika sürmüştür. Eğitilen Inception v3 modelinin ortalama model boyutu ise yaklaşık 260 MB'dır. Diğer taraftan SqueezeNet, MobileNet v1, MobileNet v2 ve GoogleNet gibi derin öğrenme ağlarının ise eğitim maliyeti olarak düşük eğitim süresine ve model boyutuna sahip olduğunu tespit edilmiştir. Benzer şekilde veri boyutu büyüdükçe, eğitim süresinin de bire bir oranda arttığı belirlenmiştir. Düşük eğitim maliyetine sahip derin öğrenme ağları arasından en iyi sonuç veren MobileNet v1 ağının eğitimi; Tiny-imagenet veri kümesi üzerinde 75 dakika, Plantvillage veri kümesi üzerinde yaklaşık 2.5 saat, temel Çanakkale veri kümesi üzerinde yaklaşık 3 dakika ve karmaşık Çanakkale veri kümesinde ise yaklaşık 12 dakika sürmüştür. Eğitilen MobileNet v1modelinin ortalama model boyutu ise yaklaşık 27 MB'tır.
Design and implementation of a novel physically unclonable function with a new cellular automata model

(Fen Bilimleri Enstitüsü, 2020) Göncü, Emre ; Yalçın, Müştak Erhan ; 657021 ; Elektronik ve Haberleşme Mühendisliği Ana Bilim Dalı

The number of devices in network increases continuously by the Internet of things (IoT) paradigm. It is expected that there will be over 25 billion devices connected to the internet, by 2025. Furthermore, IoT applications can be encountered in almost every part of our lives such as at homes, in vehicles, in human bodies. Obviously, most of those devices store sensitive data. In addition, because of the rapid increase of e-business practices, the devices realizing secure transactions of huge sensitive data are essential. Therefore, security and trustworthy of that kind of devices become more and more important. Secure transactions are realized with strong cryptographic systems. True Random Number Generators (TRNG) are essential for these systems in order to source the inputs such as keys, initialization vectors and challenges. Statistical quality of the TRNG is one of the metrics determining the security level of the system. Therefore, designing and implementing a TRNG of high quality is vital for a strong cryptographic system. Nowadays, threats of counterfeit integrated circuits (IC) arise around the world. Therefore, Intellectual Property (IP) protection of the hardware designs is one of the major challenges of IC designers. They want their hardware to run on a limited number of ICs because of commercial reasons. Physical Unclonable Functions (PUF) are another security primitives extracting the unique identity of devices from the physical characteristics. In fact, this identity is a trust anchor in higher-level security architectures. Therefore, they can answer the security challenges mentioned above. Cellular Automata (CA) are discrete dynamical systems used in many different fields like modelling, pseudo-random generation, image processing, \textit{etc.}. Since standard CA are deterministic systems, it is not possible to obtain random bit sequence at the output. However, a new CA model proposed in the thesis makes it possible by adding some physical noises to the model. Introduced model is also realized on FPGA. It is empirically proved in thesis that the output of the system is random. Employing the randomness of the new CA model, a TRNG and a PUF design are proposed in order to address the solutions for given problems above. The proposed TRNG, without any post-processing block, passes all the statistical tests provided by NIST. Furthermore, it has a higher speed regarding the other TRNG implementation on FPGAs given in the literature. PUF design is also promising by the terms of security and reliability regarding the other PUF implementations on FPGA in the literature. Finally, at the end of the thesis, a novel Application Specific Integrated Circuit (ASIC) implementation of Advanced Encryption Standard (AES) block cipher is introduced. The AES hardware is asynchronous in order to have reduced power consumption and throughput improvements regarding the other AES hardware realizations given in the literature. Furthermore, the IC is fabricated using TSMC-65 nm standard cells.
Design and implementation of an 11-bit 50 ms/s flash-assisted successive approximation register ADC

(Graduate School, 2023) Maden, Fatih ; Karalar, Tufan Coşkun ; 783612 ; Electronics Engineering Programme

Modern electronic systems transmit, store, and process data. Pure analog solutions are no longer practical due to the increasing complexity of electronic systems. Thanks to advances in digital signal processing (DSP), signal processing and storage have moved from analog to digital domains. However, first of all, analog signals should be converted to digital signal in order to take advantages of DSP. Therefore, DSP systems are needed ADC. There are different ADC topologies in the literature because each system has different performance requirement. The most popular ADC architectures are flash, pipeline, SAR, delta-sigma and time-interleaved ADCs. Each of these architecture has own advantages and disadvantages in terms of resolution, sample rate etc. SAR ADC has been one of the most widely used ADC architectures over the past decade. Due to its largely digital structure, SAR ADC take advantage from CMOS technology scaling. SAR ADCs are generally preferred for medium accuracy, medium speed, and low power applications like biosensors, image sensors, and wearable devices because they have the highest energy efficiency of all moderate bandwidth, moderate resolution converters. However, resolution and speed of the SAR ADC is restricted by comparator offset and mismatch in the DAC. Therefore, many calibration and redundancy techniques have been proposed to improve SAR ADC resolution, but they increase design complexity and don't solve bandwidth issues. In this work a new method proposed in order to increase resolution of the SAR ADC without speed degradation. 11-bit flash assisted SAR ADC with a 50 Msps date rate designed and simulated in TSMC 65nm technology node. The working principle of the our design is similar to pipeline ADC. Conversion is completed in two cycles . In the first cycle SAR ADC sample the input signal and generate the most significant eight bit. In the second cycle, the residue voltage produced by the SAR ADC is amplified through the switch capacitor circuit and converted into three bits with the help of the flash ADC. Then output of the SAR ADC and flash ADC is aligned and 11-bit resolution is obtained. The thesis consists of five chapters, with the first chapter introducing the work and objectives. In the second chapter, background information about ADC design and commonly used ADC architectures are reviewed. In the third chapter, the architecture of the designed flash-assisted SAR ADC is explained. In chapter four, simulation results for the designed blocks are presented and interpreted. The thesis is concluded and compared with similar work in the fifth chapter.
Design and implementation of high power GaN amplifiers with nonlinear optimization techniques

(Lisansüstü Eğitim Enstitüsü, 2021) Kouhalvandi, Lida ; Özoğuz, İsmail Serdar ; 671561 ; Elektronik ve Haberleşme Mühendisliği

In this thesis new and novel optimization methodologies will be prepared to design nonlinear circuits operating at high frequencies. These novel methods can be used to optimize circuits with realistic models and process design kits (PDKs). Thus, nonlinear and complex power amplifiers with wide-band and high-efficient specifications can be designed by applying the proposed optimization algorithms. The developed script runs on a computer and manages the nonlinear simulator and numerical analyzer to optimize the challenging nonlinear circuit design problems regarding the design rules and conditions set by the designer and requirements. The proposed optimization algorithms are implemented in an automated environment with the combinations of electronic design automation (EDA) tool such as ADS and numeric analyzer as MATLAB. This process decreases the dependency to any designer's experience and without any human interruption all the optimization process is performed automatically. Power amplifiers (PAs) consisting of Gallium Nitride (GaN) high electron mobility transistors (HEMTs) will be designed with the proposed optimization algorithms. The PAs' efficiency, gain response, linearity, and bandwidth will be optimized to achieve high performance results regarding the reported studies. The PAs operate at saturation mode and nonlinear region; hence, high dimensions of variables are achieved. EDA tools such as ADS, AWR, etc. include nonlinear optimizations and are successful tools in optimizing circuits; however, additional powerful optimizations are required to deal with large amount of data. Also, the commercial EDA tools face with the problems when the unreliable nonlinear models are used during the optimization process.Therefore, a need for the new simulation environment that is the combination of the EDA tool and numerical analyzer becomes essential. Regarding to the difficulties in commercial EDA tools, it becomes necessary to propose an optimization strategy suitable for nonlinear circuits to be reliable for simulating nonlinear models and also able to challenge many trade-offs of high power amplifiers (HPAs) such as efficiency, linearity and gain flatness. The scope of the proposed methods are based on scrip development for two processes: i) a scrip to control nonlinear simulator (ADS) and numerical analyzer (MATLAB), ii) algorithms to optimize the circuit parameters. These algorithms result in high performance PAs in terms of efficiency, output power, gain, and linearity. The used transistor model is GaN technology due to the several advantages for radio frequency (RF) circuits such as high power density, high thermal conductivity, large breakdown voltage, and good reliability. This technology is suitable for future applications of radar and fifth generation (5G) systems. The importance of this work is divided in to four sections: 1) Providing an automated environment that is a reliable simultaneous co-operation of EDA tool (ADS) and mathematical analyzer (MATLAB); 2) Proposing novel optimization strategy based on intelligent algorithms for RF nonlinear circuits results in best high performance; 3) Substituting the proposed novel optimization technique to the automated environment; and 4) Optimizing the whole PA designs automatically and comparing the results of fabricated PAs with the simulation outcomes.

Gözat

Başlık ile LEE- Elektronik Mühendisliği Lisansüstü Programı'a göz atma

Sayfa başına sonuç

Sıralama Seçenekleri