LEE- Elektronik Mühendisliği-Yüksek Lisans
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Sustainable Development Goal "Goal 9: Industry, Innovation and Infrastructure" ile LEE- Elektronik Mühendisliği-Yüksek Lisans'a göz atma
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Öge4 channel configurable constant-current/voltage mode biphasic implantable neurostimulator ASIC with channel centric active charge balancer(Graduate School, 2022-03-02) Cakalı, Anıl ; Karalar, Tufan Coşkun ; 504161229 ; Electronics EngineeringElectrical stimulation is a technique that let inhibition or exhibition neuron activities with charge injection to a target tissue. Neural stimulators are used as a treatment method for diseases and the restoration of dysfunctional organs. Sacral Nerve Stimulation that is used for the treatment of bladder and urinary functions, Deep Brain Stimulation (DBS) that is used for the treatment of diseases such as Parkinson's disease, epilepsy, tremor, depression, and obsessive-compulsive disorder, Spinal Cord Stimulation that is used for the treatment of chronic pain syndrome, Retinal Stimulation that is used for recovering visual functions and Cochlear Stimulation that is used to recovering of hearing functions are some of the application fields of electrical/neural stimulation. Considering application fields, most neurostimulator/neuromodulation devices are implanted in the human body. These devices are battery-powered devices that have long battery life, because of that an Application Specific Integrated Circuit (ASIC) is needed for implantable applications considering application specifications like target nerve, power consumption and output properties. Neurostimulators interface with target neurons by using electrodes. Charge accumulation on an electrode-tissue interface may cause Ph variation of electrolyte, toxic surface creation between electrode-tissue interface and variation of electrode-tissue impedance. Most importantly, it may cause permanent nerve damage. Using biphasic stimulation and active charge balancer structure together is the preferred method to achieve ideally zero net charges on the target tissue. Constant-current stimulation, constant-voltage stimulation or constant-charge stimulation methods are presented in the literature. Constant-current stimulation is the safest stimulation method. Ideally, zero net charge on tissue may be achieved by controlling anodic and cathodic current amplitudes and durations in a biphasic manner. For constant-voltage stimulation, the amplitude of current that flows through the electrode-tissue interface is determined by the impedance of the electrode-tissue interface. Due to that reason, it is not easy to control transferred charge to tissue. Constant-charge stimulation is a useful method to achieve charge balancing by using switch-capacitor structures. The disadvantage of constant-charge stimulation is that it needs larger capacitors that cause some difficulties with on-chip implementation. In literature, neurostimulator ASICs are designed for only constant-current mode stimulation or only constant-voltage mode stimulation. Similarly, most charge balancer circuits are designed for just constant-current mode stimulation or constant-voltage mode stimulation. In this work, a novel active charge balancing scheme that works with both constant-current mode and constant-voltage mode for monopolar/bipolar/tripolar/quadripolar electrode polarities is proposed. Furthermore, a novel channel circuit and novel channel centric active charge balancer circuit topologies that support both constant-current and constant-voltage stimulation mode in the same structure are developed. Constant-voltage mode stimulation is considered the standard technique of DBS applications for a long time. On the other hand, constant-current mode stimulation is emerging as an alternative solution for DBS applications. Supporting both constant-current mode and constant-voltage mode with active charge balancing makes this work appropriate for DBS applications. The purpose of this work is to increase the flexibility and safety of neurostimulators because this work allows switching stimulation mode after surgery and supplies active charge balancing for both stimulation modes for safety. Neurostimulator ASIC is constructed by 4 channels. Each channel consists of N-Block, P-Block and Channel Centric Active Charge Balancer. Each channel is configurable to supply ground, 10 V, 0-1 mA configurable sink current or 0-1 mA configurable source current in constant-current stimulation mode. Each channel is configurable to supply ground, 10 V, 1-5 V configurable low voltage or 5-9 V configurable high voltage in constant-voltage stimulation mode. N-Block circuit is designed to supply ground, 0-1 mA configurable sink current or 1-5 V configurable low voltage. P-Block circuit is designed to supply 10 V (as VDD), 0-1 mA configurable source current or 5-9 V configurable high voltage. Stimulation period, anodic phase time and interphase delay time are configurable parameters. Cathodic phase duration is not configurable because it is controlled by using outputs of Channel Centric Active Charge Balancer asynchronously. N-Block and P-Block circuits are similar to each other and complementary structures. The supply voltage of the stimulator circuit was chosen as 10 V to prevent headroom problems. Considering high voltage supply requirements, the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 um Bipolar-CMOS-DMOS (BCD) technology process was chosen. Relatively high biasing currents and enable/disable circuits were used for analog blocks to achieve higher performance with lower power consumption. The actual channel current is estimated by using differences of internal currents. Internal currents are mirrored to channel centric active charge balancer circuit to estimate channel current and use it for charge balancing. Timing setting resolution was chosen as 1 us. All analog blocks that are used in N-Block and P-Block were designed in Cadence Virtuoso considering timing, voltage and process constraints. DC, AC, transient and stability simulations were run to verify analog subblocks with Cadence Spectre. Transient simulations were run to verify constant-current stimulation mode and constant-voltage stimulation mode behaviors of N-Block and P-Block. Maximum current error results for constant-current stimulation, maximum voltage error results for constant-voltage stimulation and channel current estimation error results for both stimulation modes are given as simulation results. Channel centric active charge balancer was designed with Cadence environment. Transient simulations were run considering stimulation duration and current amplitude boundaries to verify functionality and determine performance with Cadence Spectre. Charge errors are presented as simulation results. Register Transfer Level (RTL) design of the stimulator controller was designed with Verilog Hardware Description Language (HDL). Synchronous state machines are used to implement the stimulator controller. Asynchronous digital circuits are used to handle outputs of active charge balancer circuits. The stimulator controller was synthesized by using Cadence Genus tool. Place and route process was performed by using Innovus tool. Digital blocks were integrated with analog blocks in Cadence Environment and Analog-Mixed Signal (AMS) simulations were run to verify the behavior of the neurostimulator ASIC for constant-current and constant-voltage stimulation modes with random test vectors. As a conclusion, 4 channel configurable constant-current/voltage mode biphasic implantable neurostimulator ASIC with channel centric active charge balancer was verified by using AMS simulations for both constant-current and constant-voltage stimulation modes. AMS simulation results show that the ASIC works functional and the proposed channel centric active charge balancing scheme is verified for both stimulation modes.
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ÖgeAc-coupled supply modulator desıgn ın 130 nm PD-SOI technology(Graduate School, 2023-06-14) Barin, Furkan ; Tekin, Ahmet ; Zencir, Ertan ; 504201216 ; Electronics EngineeringHigh peak-to-average values (PAPR) of modern telecommunications standards tend to drop the efficiency of the power amplifiers. The drop in efficiency causes excessive power consumption, which leads to a shortened battery life for mobile systems. As a result, envelope-tracking supply modulator (ETSM) systems are developed to improve power amplifier efficiency by varying their supply voltage. There are different envelope-tracking supply modulator topologies in the literature that combine different amplifier structures with each other. The most popular topologies can be considered hybrid topologies, which take advantage of using two amplifiers in parallel with each other. This hybrid structure allows high-frequency components to be provided by the linear amplifier while low-frequency power is provided by a highly efficient switching amplifier. The linear amplifier is generally designed with a Class AB output driver, which increases the driving capability and reduces the power consumption of the linear amplifier. A buck converter is mostly used as a switching amplifier to generate DC current for the load. In the literature, a hysteretic control loop is commonly used to control the buck converter with the linear amplifier, and an additional dc-dc converter is added to control the supply voltage of the linear amplifier. To improve efficiency, AC-coupled hybrid topologies are introduced to lower the power consumption of the linear amplifiers. In this thesis, an AC-coupled hybrid ETSM is designed for 5G cellular vehicle-to-everything (C-V2X) systems that support up to 40 MHz of baseband bandwidth. The system consists of a proposed operational amplifier, a switching amplifier, a current-mode hysteretic buck converter to control the supply of the linear amplifier, a proposed zero-current detection (ZCD) current to detect the reverse current flowing through the inductor, and low-dropout regulators (LDO) for supplying the internal analog circuits. The ETSM is implemented in a 130 nm partially depleted (PD) silicon on insulator (SOI) process, and the die size is 3.051 mm2.
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ÖgeFPGA üzerinde 5G uyumlu düşük yoğunluklu eşlik denetim kod çözücü gerçeklenmesi(Lisansüstü Eğitim Enstitüsü, 2022-09-12) Bilgili, Barış ; Örs Yalçın, Sıddıka Berna ; Pusane, Ali Emre ; 504191203 ; Elektronik MühendisligiGünümüzde giderek artan sayısal veri üretimi ve veri ihtiyacı, bu verilerin iletilebilmesi için yüksek hızlı kablosuz haberleşme sistemlerini giderek daha önemli hale getirmektedir. Taşınan veri miktarının artması yeni gereksinimleri de beraberinde getirmektedir. Bunlardan ilki haberleşmenin daha hızlı yapılabilmesidir. İkincisi ise bu verilerin kanaldaki bozulmalardan etkilenmeden alıcı tarafa iletilebilmesidir. Haberleşme insanlar veya makineler arasında gerçekleşse de, hücresel ağlar veya uydu üzerinden sağlansa da yeni gereksinimler eklenebilmesine rağmen bu iki gereksinim değişmemektedir. Bu noktada üretilen standartlar belirtilen gereksinimleri karşılamaya çalışmaktadır. Hücresel haberleşme için güncel bir standart olan 5G'de ileri hata kodlama olarak Düşük Yoğunluklu Eşlik Denetim (Low Density Parity Check - LDPC) kodları veri kanallarındaki bu gereksinimleri karşılamak için önerilmiştir. Uydu haberleşmesinde ise İkinci Nesil Sayısal Video Yayını (Digital Video Broadcasting - DVB S2) gibi standartlarda LDPC kodları kullanılmaktadır. LDPC kodları yapıları itibariyle esnek tasarım ve uygulamalara uygun kodlardır. Farklı blok boylarında ve paralel çalışmaya elverişli oldukları için Alanda Programlanabilir Kapı Dizileri (Field Programmable Gate Array - FPGA) ile gerçeklenmeleri avantajlı bir hale gelmektedir. LDPC kodları farklı kod çözme algoritmalarıyla çalışabildikleri için FPGA gerçeklemeleri yapılmadan önce bu algoritmalar performans ve gerçeklemeye uygunluk açısından incelenmelidir. Kod çözücünün düşük alan kullanımına ve yüksek veri hacmine sahip olması gerektiği için buna uygun bir algoritma seçilmelidir. LDPC kodları genellikle bir eşlik denetim matrisi ile tanımlanırlar. Kod çözücü tasarımında bu matris, veri depolama birimlerinin boyutlarını ve bağlantıları belirler. Kod çözücüde algoritmanın çalıştığı asıl birim ise Denetim Düğümü Birimi ( Check Node Unit - CNU) olarak tanımlanır. Bu çalışmada 5G Yeni Radyo (5G New Radio - 5G NR) standardı temel alındığı için veri boyutları ve bağlantıları büyük oranda belirlidir. Algoritma seçimi, paralelleştirme ve veri hacmini arttırma üzerine çalışmalar yapılmıştır. Donanım gerçeklemesi yapılırken karşılaşılan veri depolama, adresleme ve sıralama sorunlarına çözümler üretilmeye çalışılmıştır. Döngüde FPGA (FPGA in the Loop - FIL), FPGA'de çalışması için bir donanım tanımlama diliyle (Hardware Description Language - HDL) yazılmış kodları MATLAB ortamı ile entegre ederek gerçek donanım üstünde çalışan kod ile yazılımdaki kodların beraber benzetiminin yapılması sağlayan doğrulama programıdır. HDL ile tasarım yaparken doğrulama yapmak çok önemli bir yer tutmaktadır ve FIL kullanılmadığı durumda herhangi bir bloğun doğrulamasını yapmak için test dosyaları oluşturup veri grupları hazırlayarak benzetim yapılması gerekmektedir. FIL sayesinde MATLAB ortamında oluşturulan veriler örnek modelle aynı anda gerçek donanım üzerinde çalışan HDL koduyla kıyaslanarak sonuçları doğrulanabilmektedir. 5G NR standardındaki LDPC matrisleri farklı boyutlara ve farklı satır ağırlıklarına sahip oldukları için bu çalışmada tasarlanan LDPC eşlik denetim biriminin farklı sayıda giriş ile çalışabilmesi gerekmektedir. Bu nedenle FIL kullanılarak farklı sayıda girişler için MATLAB ortamında doğrulama yapılmış ve FPGA üzerinde çalıştırılarak test edilmiştir. Bu çalışmada hem FIL ile doğrulama yaparak tasarım ve doğrulama süreçlerinin hızlandırılması, hem de donanıma uygun algoritmalar seçilerek karmaşıklığı düşük ve veri hacmi yüksek bir eşlik denetim birimi tasarlanması, eşlik denetim biriminin çalışmasına örnek göstermek amacıyla 5G NR standardına uygun bir üst seviye tasarımının yapılması amaçlanmıştır.
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ÖgeGF 22nm FDSOI power management unit with integrated SRAM design(Graduate School, 2023-01-05) Çoban Mahmut ; Tekin, Ahmet ; 504201269 ; Electronics EngineeringThe primary objective of the research presented in this dissertation is to design PMU and SRAM circuits for space and lidar applications. This PMU block is able to provide the whole power supply necessary for any SoC application, even in harsh temperatures (i.e., 150 °C), making it appropriate for space applications, and it can only do so by acquiring a worldwide supply. In addition, this worldwide supply has a wide range, ranging from 1.8V to 3.6V. Unique in that it automatically adjusts itself across this full range. Furthermore, despite offering all these advantages, it never sacrifices its economy or performance standards. The thesis is structured as follows: In Chapter 2, the stages from the fundamental information about the SRAM architecture to the design of the structure anticipated to be employed in the project will be discussed. This chapter will also feature the simulation findings from SRAM. The SRAM array system is built with GF Fully Depleted Silicon on Insulator (FD-SOI) 22nm CMOS technology and a 0.85 V power supply. According to the DC characteristic curves of the SRAM cell, the SNM is 0.216 V during the read operation and 0.383 V during the write operation. Read and write operations are performed at a rate of 2 GHz. The entire power consumption is 3.6 mA, and the total layout area is 0.213 x0.273 µm x µm. In Chapter 3, the fundamental supply sources that will be utilized in the Buck Converter and supplying the analog blocks in the PMU, which we refer to as the internal PMU, will be analyzed in depth. Detailed simulation results and their interrelationships will be presented. The internal power management sub-blocks will be discussed. These blocks are a Bandgap Reference circuit (BGR) and three different Low-Dropout regulators (LDOs): a protected high-voltage LDO, a companying always-ON auxiliary LDO and a current sink LDO for power converter level shifters. The system power supply ranges from 1.8 V to 3.6 V, so that it can be used for a wide range of tasks. The system automatically adjusts itself according to the provided supply level. The BGR produces a process, supply voltage, and temperature (PVT), a stable reference voltage, and current to produce bias for high-voltage LDO and other system blocks. The high-voltage LDO takes in a wide range of input supply voltages and always produces 1.8V output. The sink LDO generates the tracking level shifter voltage for digital driver circuits and adjusts automatically according to supply voltage to keep transistors in the Safe Operating Area (SOA). The auxiliary BGR and auxiliary LDO are extremely low power, and they used to overcome "chicken-and-egg" problems by providing a coarse, always-on output level that was overtaken by the main LDO when the system was powered up. The proposed project is designed and simulated in a 22-nm FD-SOI, and the layout area is 292.4 µm x 98.3 µm. In Chapter 4, we'll talk about the Buck Converter, which is the last part of the PMU. It will provide the Buck Converter's employed methodology, circuits, and simulation results. This section talks about a dual-mode DC-DC buck converter with a gate size control that can be changed based on the load current for digital systems or systems where noise doesn't matter. For light-load applications, a selective adaptive on-time pulse frequency modulation (PFM) control is presented to achieve maximum power efficiency by determining the optimal switching frequency based on the load current, thereby minimizing unneeded switching losses. When the inductor peak current value or converter output voltage ripple is taken into account, the on-time can be modified further in some cases. In heavy-load applications, a typical control method called pulse width modulation (PWM) is used with power gates that can be changed to make sure efficiency over a wide range of currents. A dual-mode buck converter prototype is simulated using a 22 nm CMOS FDSOI technology, attaining a reported 92.0% efficiency across the current range from 10 mA to 8 A. The conclusion is found in Chapter 5. This chapter summarizes the research's results and contributions. The audience is also told what kind of research might be done in the future based on what has already been found.
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ÖgeRange profile extraction in noise radars based on the target characteristics(Graduate School, 2023) Çaha Karabağ, Şevval ; Selçuk Paker ; 777760 ; Elektronik-Haberleşme Eğitimi Ana Bilim DalıContinuous and pulsed radar systems are frequently used in military and civilian applications. The detection capability of a radar depends on the antenna properties used, the size and material properties of the target to be detected, the noise level of the receiving antenna and the RF line, and the effective output power of the radar, which is one of the most important. The effective output power of radar systems increases in direct proportion to the pulse width, thus improving the signal-to-noise ratio (SNR). A high SNR level improves detection performance and measurement accuracy. However, in conventional pulse radar, increasing the pulse length causes a decrease in the range resolution, which is undesirable. Different types of pulse compression are used to achieve high output power and low range resolution. These include frequency modulation and phase modulation. One of the most popular frequency modulations is the pulse compression technique based on linear frequency modulation. In phase modulation, which is another method, the phase of the radar pulse can be generated by different intrapulse modulations such as binary phase modulation, poly-phase modulation, and noise or pseudo-noise modulations. Phase-modulated waveforms are obtained by dividing a pulse into multiple sub-pulses to achieve the required main lobe and side lobe levels. The length of a single sub-pulse obtained defines the radar's range resolution.