LEE- Elektronik Mühendisliği-Yüksek Lisans

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http://hdl.handle.net/11527/19264

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Mobil batarya enerji depolama sistemleri kullanılarak dağıtım sistemi işletiminin iyileştirilmesi ve sistem üzerindeki etkilerinin analizi

(Lisansüstü Eğitim Enstitüsü, 2021) Karahan, Oğuzhan ; Bağrıyanık, Mustafa ; 705347 ; Elektrik Mühendisliği Ana Bilim Dalı

Gün geçtikçe nüfus artışı ile birlikte teknolojinin de ilerlemesi, elektrik enerjisine olan ihtiyacı artırmıştır. Güncellenen dünyada, elektrik enerjisinin optimum kullanımı için çok çeşitli planlamalar yapılmaktadır. Önceki yıllara ait veriler kullanılarak ileriye dönük kısa veya uzun vadeli enerji tahminleri yapılmaktadır. Elektrik enerjisinin üretiminden tüketimine kadar her kademesinin optimum bir şekilde çalışmasını sağlayan birçok Enerji Yönetim Sistemi (EYS) vardır. Elektrik enerjisinin üretiminde birçok farklı kaynak kullanılmaktadır. Günden güne artan elektrik enerji ihtiyacı, sınırı olmayan enerji üretim kaynaklarının kullanımını arttırmaktadır. Güneş ve rüzgar gibi kaynaklardan elektrik enerjisinin üretildiği Yenilenebilir Enerji Sistemi (YES) birimleri yaygınlaşmaktadır. Elektrik enerjisi yüksek gerilim kademelerinde iletilerek son tüketiciye dağıtım sistemleri aracılığıyla ulaştırılmaktadır. Elektrik dağıtım sistemleri, birçok şebeke yapısıyla işletilebilmektedir. Sistemdeki tüketicinin sayısına ve profiline uygun olarak farklı şebeke yapıları kullanılmaktadır. Elektrik enerjisi üretildiği an tüketilmesi gereken bir enerji türüdür. Ancak, planlamalara uymayan sonradan eklenen yükler ve arıza durumlarında sisteme yardımcı bir güç kaynağı destek vermelidir. Bu noktada, Enerji Depolama Sistemi (EDS) birimleri önemli rol oynamaktadır. Enerjinin depolanma teknolojisine göre birçok çeşidi bulunan EDS'lerden bu çalışmada, Batarya Enerji Depolama Sistemi (BEDS) incelenmiştir. Elektrikli araçların artması ile birlikte batarya teknolojisine ilgi artmıştır. Yenilenen batarya teknolojisi, farklı kapasitelerde enerji depolanması fırsatı sunmaktadır. Kullanılan batarya türüne ve hareket etme özelliğine göre farklı türleri bulunan BEDS'ler, EYS'ler için önemli bir araç haline gelmiştir. Hareket etme özelliğine göre sabit ve mobil olmak üzere iki çeşidi bulunan BEDS'lerin birçok avantajı bulunmaktadır. Çoğu uygulama alanı ortak olsa da hareketli olma özelliğinden dolayı Mobil Batarya Enerji Depolama Sistemi (MBEDS)'nin kullanım alanı daha fazladır. Elektrik enerjisi üretim-dağıtım ağındaki çoğu birim için çeşitli faydaları bulunmaktadır. Gelişimi devam eden güncel teknoloji olan MBEDS'ler için literatürde birçok çalışma vardır. YES birimlerinin kesintili enerji üretimi nedeniyle bulundukları güç şebekesine MBEDS'ler ile entegre edilmektedir. Hareketli olma özellikleri sayesinde güç şebekesinde herhangi bir kısa devre arızası anında şebekeye ada işletimi sağlayabilmektedirler. Dağıtım sistemlerine entegre edildiklerinde gerilim düşümü ve güç kaybı gibi sistem parametrelerine etki etmektedirler. Günün herhangi bir anında meydana gelen puant yükü azaltmak için MBEDS'ler kullanılabilmektedir. Böylece tampon görevi üstlenerek güç şebekesi rahatlatılmaktadır. Elektrikli araçların şarj istasyonları olma görevi de edinebilmektedirler.
High sensitive torque control of permanent magnet synchronous motor for national military applications

(Graduate School, 2021-07-26) Köse, Mehmet Eralp ; Kocabaş, Derya Ahmet ; 504181249 ; Electronics and Communication Engineering ; Elektronik ve Haberleşme Mühendisliği

Electric motors are systems that convert electrical energy into mechanical energy, and they have a very important place in the industry. DC motors are often preferred for applications that do not require driving precision due to their ease of use and low cost. On the other hand, alternating current motors have many superior features over direct current motors. Alternating current motors have higher efficiency, lower maintenance costs, and high torque to volume ratio. They are more reliable and durable motors. One of the most important advantages of alternating current motors is that they offer superior motor control opportunities. With these motors, speed and torque control can be done with appropriate control methods. With the appropriate control method, torque control can be done at very low speeds. Because of these features, alternating current motors are preferred in control applications that require precision. With the developing magnet technology, permanent magnet electric motors come to the fore with their high efficiency. Power electronics and control applications are used together for the control of alternating current motors, and there are different methods and circuit structures in the literature for this. Control methods are basically divided into two as scalar and vector control. In scalar control, the "voltage/frequency" ratio is kept constant so that the flux remains constant, and the speed and torque are adjusted with the change in frequency. In this method, only the magnitudes of flux and current are controlled, rotor position information is not received as feedback and is not included in the control loop. In vector control, in addition to the magnitude of the flux and the current, the angle between them is also controlled, and rotor position information is required as feedback while speed and torque controls are being made. Direct torque control and field-oriented control are sub-branches of vector control. In field-oriented control, which is the focus of this study, the rotor position is needed. This information can be obtained with sensors, or it can be detected by sensorless estimation methods, and position information is used in control. In this way, while precise speed and torque controls are carried out, a more stable control is provided in a steady-state condition. In this thesis, high precision torque control of permanent magnet synchronous motors for use in military systems has been studied. The main goal is to design motor drivers that are imported and provide torque control in military stabilization systems and to reduce foreign dependency by using domestic and national motor drivers in these systems. Since high precision torque control is aimed even at low speeds in military applications, field-oriented control was used. Due to the high military expectations, sensor control was preferred, and an absolute encoder was preferred as a position sensor. This method can be applied in many areas with different power and torque requirements. Stabilization systems were chosen as the application. Based on filed-oriented control, a national control algorithm has been applied, and an infrastructure adaptable to the power and torque requirements of the application to be used has been established. In this context, TMS320F28069M type numbered processor from Texas Instruments (TI) company, and the trial card was used as controller. Inverter design is implemented with modular circuits of TI company, and MOSFET switches are used. Algorithm development studies were carried out in MATLAB/Simulink environment. An absolute encoder is used to increase sensitivity. With this encoder, absolute position information can be accessed and position information is not lost even if there is a power cut. The position information obtained from here is transferred to the field-oriented torque control loop. By carrying out the load test, the moment ripple in the steady-state and its performance at the rated load have been determined. Different communication methods have been used to determine the interaction of the performance of the system. Since it was seen that the method called "external mode" which works over Simulink, became insufficient and did not work efficiently as the algorithm became more complex, CAN communication was started, and it was ensured that the instantaneous torque value could be controlled with the P and I coefficients that can be changed instantly via the PI controller. Input and output feedbacks were instantly observed via Simulink, algorithms were written in Simulink, and all hardware was communicated with Simulink via CAN communication. The effect of switching frequency on torque ripple was investigated with appropriate P, I coefficients, and as a result of the optimization, this ripple was reduced below the values expected by the standards. In the second part of the study, compliance checks were made in terms of military standards, and temperature and electromagnetic compatibility tests were completed. Since a device with a chassis was not aimed directly, mechanical compatibility tests were not needed. Temperature tests were carried out between -40°C and +55°C in accordance with the standards, and the distortions observed in the clock frequency of the processor at values close to the limit temperatures in the first tests were overcome by the use of an external oscillator. Although an increase in torque fluctuation was observed in this test, the maximum value remained below 3%. In electromagnetic compatibility tests, MIL-STD 461 CE101 and CE102 tests were carried out, and the noise emitted by the device in various frequency ranges was measured. Although the noise remained above the acceptable level in the first CE102 test, the circuit passed the tests successfully with the appropriate filter design. In addition, with the study, infrastructure was created for the selection of materials for further studies. As a result, within the scope of this thesis, low torque vibration, high precision field-oriented torque control of a permanent magnet synchronous motor in accordance with military temperature and EMC standards have been realized. With the output of the thesis, domestic equivalents of hardware and software products supplied from abroad and used in national applications have been obtained, contributing to the country's economy and reducing foreign dependency in this area.
Hard and soft tissue characterization with microwave dielectric spectroscopy

(Graduate School, 2022) Keskin, Seda ; Akgül, Tayfun ; 741159 ; Department of Electronics and Communication

The dielectric property discrepancy between hard and soft tissues at microwave frequencies can potentially be utilized for the separation of those tissues from each other. Microwave dielectric properties of biological tissues are traditionally measured with the open-ended coaxial probe technique. However, the technique suffers from high error rates thanks to tissue heterogeneity, user errors, mathematical approach, and calibration degradation. It is known that datasets with different values will be classified with high accuracy when a machine learning algorithm is applied. Therefore, choosing a classification parameter that might be least plagued by inherent errors is critical for increasing the accuracy of tissue categorization. Empirically, dielectric properties at microwave frequencies abide by the power law. Supported this fact, one unexplored parameter is the power parameter which might be derived from the dielectric properties. This work presents investigations on the potential use of the power parameter to separate different tissues, spesifıcally hard and soft tissues, supported by the datasets within the literature. Additionally, to research the effectiveness of the power parameter, classification was performed with machine learning algorithms using the power parameters obtaıned from dielectric property measurements of healthy and malignant liver tissues. Through the appliance of the technique 82% accuracy was obtained. Towards this goal, it's predicted that the power parameter might be used as a feature containing different information additionally to dielectric properties in tissue classification. Alternatively, in some cases dielectric properties do not provide enough information, one example is that the separation of hard and soft tissues, under such conditions the power parameter might be employed for classification purposes. This approach might be used as an alternative method for rapid diagnostic to high-cost imaging or mutation screening tests. The frequency-dependent dielectric properties of the biological tissues are crucial to developing diagnostic technologies.
Design of an OPAMP-RC lowpass filter in 22 NM FDSOI technology

(Graduate School, 2022) Keleş, Ömer Taha ; Yazgı, Metin ; 734685 ; Electronics Engineering Programme

Analog filters are widely used in signal processing applications like noise reduction, blocker rejection, signal detection, anti-aliasing, demodulation, audio processing etc. They are utilized to allow certain signals to pass while blocking others. Passed or blocked signals are not time dependent since analog filters are time invariant circuits. These filters pass or block signals depending on the signal's frequency, meaning that signals in specified frequency ranges are blocked or passed. While time domain responses of the filters are still a critical design consideration, filters are mainly designed considering the desired frequency domain responses. Main types of filters can be categorized as lowpass, highpass, bandpass and bandstop according to their selective frequency range. There are various types of lowpass filter responses which have different passband or stopband characteristics. Brick wall response, whose pass and stop bands are separated at the corner frequency, has a discontinuous frequency response. This type of a mathematical function is not realizable in real world. On the other hand, realizable filter responses are continuous functions with finite roll-off slopes between stopband and passband. The slope at the transition band depends on the order of the filter function and the type of the filter function. Additionally in real filter functions there may be permitted fluctuations which may appear in stopband, passband or both. In Butterworth response, the passband has flat frequency characteristics so it is called maximally flat magnitude response. Likewise, Chebyshev type I filter response has equal ripples in the passband so it is called equal ripple magnitude response. Chebyshev type II filter response, or equal ripple stopband magnitude response, has equal ripples in the stopband and Cauer filters have ripples in both stopband and passband. The question of how to realize filter functions with real circuit elements arises numerous solutions. Such filter functions can be realized using circuit elements like resistors, capacitors, inductors and some specialized circuit elements such as operational amplifiers and switched capacitors. Filter characteristics and design limitations vary greatly depending on the circuit elements and topologies used. In order to realize lowpass filter functions, various different circuit topologies are proposed over the last couple of decades. Filters are classified depending on the circuit elements employed. LC ladder filters consist of inductors, capacitors and resistors which are all passive elements. Besides resistors and capacitors, Opamp-RC filters utilize active circuit elements called operational amplifiers. Moreover, OTA-C filters are implemented using operational transconductance amplifiers and capacitors. Furthermore, capacitors, operational amplifiers and switched capacitor circuits are used to build switched capacitor filters. All the different circuit topologies have their advantages and disadvantages. It is the designer's job to determine which topology is a better choice considering the design specifications and limitations. Over the years, shrinking of transistor sizes resulted in reduced analog performance and lower voltage headroom.
Classification of chest X-rays by divergence-based convolutional neural network

(Graduate School, 2022) Kılıç, Muhammed Nur Talha ; Ölmez, Tamer ; 731698 ; Electronics Engineering Programme

The importance of imaging methods in the field of health is increasing day by day with the opportunities provided by technology. Imaging without physical intervention is both more convenient and less costly for the patient and one of the ways to diagnose faster. Diagnosis of diseases and taking action, especially in the early stages of epidemic diseases, are among the most effective methods in the fight against these diseases. Correct treatments are applied against diseases that can be differentiated from each other, thus the patient's recovery is ensured. Chest radiographs are also one of the most frequently used methods in the field of imaging, and the damage caused by various viruses or bacteria to the lung can be understood and diagnosed with X-ray images. At the same time, it ensures that health systems continue with minimum damage by providing the necessary data for health workers to take precautions in case of an infectious side of the disease. Covid-19, which entered our lives towards the end of 2019 and caused the death of millions of people in more than 2 years, directly damages the lungs and causes the lungs to not perform their functions. Problems that occur in the lungs by reducing oxygen saturation cause many issues, especially respiratory problems in patients. Some of the problems seen in patients with suspected Covid-19 occur in the lungs and these changes caused by the disease can be detected by X-rays. However, it is not known to what extent the effects of viruses such as Covid-19, which have been in existence for years but have the capacity to infect people in the near future, and it is not possible to deliver treatment techniques to all parts of the world in a short time. In other words, it is a very long and laborious process to be able to effectively diagnose diseases that we can call new diseases that come into our lives by health workers around the world. For this reason, engineering applications in the field of medical imaging are promising in many respects. For example, AI-assisted engineering applications, which have become very common recently, bring many advantages. These achievements can be listed as follows: •Detailed analysis opportunity •Instant access to developments in the world •Ability to be easily updated •Possibility to get results with high accuracy and fast •To alleviate the burden of healthcare workers •Cost-reducing contributions with fewer employees •Reaching areas with low or limited access to the health system •Reducing the contagious risk of the disease by reducing direct or indirect contact with patients •Creating systems whose accuracy and reliability are increasing day by day with continuously trained models. •Opportunity to create models trained with more examples than specialist doctors can see throughout their career Although the developments mentioned are undeniably positive, the physical hardware needs that come with artificial intelligence supported applications should not be ignored.
Analysis and design of cryogenic bulk-driven analog integrated circuits

(Graduate School, 2022) Ormancı, Mehmet Aytuğ ; Yelten, Mustafa Berke ; Kaçar, Fırat ; 737869 ; Electronics Engineering Programme

Today, exponentially increasing studies such as quantum electronics, asteroid and planet observations, and even space mining have increased the need for electronic circuits that can operate under extreme conditions without error. Circuits that can operate without consuming much power, especially in space conditions, allow for more or uninterrupted observations and measurements. The operating conditions for circuits operating in space are extreme. It is essential that the designs made for these circuits, which must operate in both high radiation and very cold conditions, produce accurate results because space is still a very costly environment in terms of research and observation costs. In this case, it is important to correct the errors in the designs at the simulation stage. The concept of a cryogenic environment defines the temperature values of 120 K (−153 ℃) and below, although the exact limits are not clear. This is because this temperature includes the boiling points of the main atmospheric gases. The design at cryogenic temperatures is indispensable for space exploration and quantum computers. Liquid nitrogen environment (LNT) is the most common method used to model cryogenic environments on the earth's surface and in laboratories and to develop circuits operating in space conditions. Nitrogen, which has a boiling point of approximately 77 K, contains most of the critical situations that electronic circuits encounter in space conditions. The operating range for integrated circuits traditionally based on common design models such as BSIM is between −55 ℃ and +125 ℃. However, when the design results made with these models are examined, it is observed that the error rate increases even moving away from the room temperature. This makes it inevitable to use new models for cryogenic conditions. The cryogenic modeling process used in this thesis is based on the logic of recalculating and replacing temperature-sensitive parameters and sub-parameters in the BSIM by using a MATLAB environment with a new algorithm. In this way, the margin of error in the experimental measurements is considerably reduced and this environment is accurately simulated in computer-aided programs. In experiments with many transistors in the cryogenic environment, it has been observed that the threshold voltage increases, but the current flowing capacity of the transistors increases as the mobility of the carriers rises. In addition, in the theoretical and practical studies, the linear reduction of thermal noise, which is seen as the main source of the noise in transistors, with temperature is promising results for the designers. With the developing electronic technology, the use of portable devices and biomedical sensors has become quite common. This brings the need for more efficient use of batteries, which cannot develop at the same rate. For this reason, the electronics industry turns to devices that work with less than 1 V power supply and consume very little power. One of the circuit design methods with a very low power supply is bulk-driven (BD) structures. Thus, when the gate terminals are biased with a DC voltage that creates a channel between the source and the drain, the current passing through the channel can be manipulated by the input signal applied from the bulk. In terms of the circuit designs, this method means removing the threshold voltage from the signal path. The most important advantages of the bulk-driven transistors can be shown as having much more linear transconductance and much less power consumption. In addition, without using n-channel and p-channel transistors together, the input common-mode range (ICMR) and output swing can be rail-to-rail. However, driving the transistor from the bulk also brings some disadvantages. The most important issue is the bulk transconductance is quite low compared to the gate-driven counterpart. Although it is theoretically possible to increase, it can activate the parasitic Bipolar Junction Transistors (BJT) in the structure and damage the chip. Also, low transconductance increases the noise factor of transistors. Another detriment is the high capacitive effects on the body. These effects greatly reduce the transition frequency of transistors. Another low power circuit design method is to operate the transistors in the subthreshold region. Transistors enter the subthreshold saturation region between 3 and 4 times their thermal voltage and can operate with low power supplies. Operational transconductance amplifiers (OTA), which are one of the indispensable building blocks of analog designs, are frequently used in analog signal processing, thanks to the high-level linear transconductance and stable high frequency performance. In this study, a three-stage OTA is designed in which all transistors operate in the subthreshold saturation region. It consists of an input stage based on non-tailed differential amplifiers, a second stage with a common-source amplifier, and a class AB output stage. The input stage provides high ICMR and 36 dB DC gain. The bias current of this structure was calculated as 8 nA using thermal noise and dynamic range in the voltage follower configuration.
Deep learning based fruit and vegetable recognition for android pos devices

(Graduate School, 2022-01-17) Ekici, Ege ; Güneş, Ece Olcay ; 504181209 ; Electronics Engineering

With the recent improvements in technology, time and expense-saving products have gained an important trend in marketplaces. Recent increases in shopping trends created a need for faster payment technologies. Even though the barcode system is currently one of the most popular technologies being used, this system is not fault-tolerant and likely to be inefficient for unpackaged products by being human dependent. As an example, fruits and vegetables are two of the most popular unpackaged product categories that are being priced based on the amount bought and cashiers usually enter a product code manually in case of purchase. Along with that, some businesses have installed self-checkout tables where customers can handle their own payments to decrease shopping time in rush hours and save on employee expenses. But self-checkout tables depend on customer trust when it comes to unpackaged products since any customer can select a product of a different price from the list. At the same time, self-checkout tables are very costly for most businesses. As a solution to the aforementioned problems, a system is proposed in this project that aims to benefit in security, expense, and time. The system aims to be advantageous by not creating an additional hardware expense by using the Point of Sale (POS) devices that most businesses already have. Focusing on fruits and vegetables, a recognition system is added using the device camera to prevent human-dependent security problems of the existing systems. Various techniques are experimented with to achieve a real-time system. In this project, a dataset consisting of 14 types of packaged and unpackaged fruits and vegetables is used. Related works usually implemented object classification and object recognition algorithms for similar problems but since objects can exist in different locations and amounts on a frame, an object recognition algorithm is decided to be more suitable for this project. Along with object detection algorithms being more complex than object classification algorithms, having POS devices with limited resources created a risk of the device being insufficient against the high computational needs of the system. For this reason, decreasing the model size and making the model closer to real time by decreasing the computation time became one of the purposes of this project. Therefore, among the object detector methods, it is decided to select a one-shot detector model. "You Only Look Once (YOLO)" is one of the state-of-the-art one-shot algorithms and is a well-known algorithm that has several versions developed over years. In this project, two of the latest versions; YOLOv4 and YOLOv5 are used and compared under several performance metrics and the best results are obtained with YOLOv5 with a mAP score of 98%. Later, several quantization methods are examined and compared for the purpose of creating a model of smaller model size and better performance. Among the quantization methods, best results are achieved with Full Integer Quantization, and model size is decreased by 75%. The proposed detection model is deployed on an android-based 400TR POS device developed by Token Financial Technologies with MT8167A (1.5 GHz) CPU. On the final system, inference time is observed as 1.332 seconds.
4 channel configurable constant-current/voltage mode biphasic implantable neurostimulator ASIC with channel centric active charge balancer

(Graduate School, 2022-03-02) Cakalı, Anıl ; Karalar, Tufan Coşkun ; 504161229 ; Electronics Engineering

Electrical stimulation is a technique that let inhibition or exhibition neuron activities with charge injection to a target tissue. Neural stimulators are used as a treatment method for diseases and the restoration of dysfunctional organs. Sacral Nerve Stimulation that is used for the treatment of bladder and urinary functions, Deep Brain Stimulation (DBS) that is used for the treatment of diseases such as Parkinson's disease, epilepsy, tremor, depression, and obsessive-compulsive disorder, Spinal Cord Stimulation that is used for the treatment of chronic pain syndrome, Retinal Stimulation that is used for recovering visual functions and Cochlear Stimulation that is used to recovering of hearing functions are some of the application fields of electrical/neural stimulation. Considering application fields, most neurostimulator/neuromodulation devices are implanted in the human body. These devices are battery-powered devices that have long battery life, because of that an Application Specific Integrated Circuit (ASIC) is needed for implantable applications considering application specifications like target nerve, power consumption and output properties. Neurostimulators interface with target neurons by using electrodes. Charge accumulation on an electrode-tissue interface may cause Ph variation of electrolyte, toxic surface creation between electrode-tissue interface and variation of electrode-tissue impedance. Most importantly, it may cause permanent nerve damage. Using biphasic stimulation and active charge balancer structure together is the preferred method to achieve ideally zero net charges on the target tissue. Constant-current stimulation, constant-voltage stimulation or constant-charge stimulation methods are presented in the literature. Constant-current stimulation is the safest stimulation method. Ideally, zero net charge on tissue may be achieved by controlling anodic and cathodic current amplitudes and durations in a biphasic manner. For constant-voltage stimulation, the amplitude of current that flows through the electrode-tissue interface is determined by the impedance of the electrode-tissue interface. Due to that reason, it is not easy to control transferred charge to tissue. Constant-charge stimulation is a useful method to achieve charge balancing by using switch-capacitor structures. The disadvantage of constant-charge stimulation is that it needs larger capacitors that cause some difficulties with on-chip implementation. In literature, neurostimulator ASICs are designed for only constant-current mode stimulation or only constant-voltage mode stimulation. Similarly, most charge balancer circuits are designed for just constant-current mode stimulation or constant-voltage mode stimulation. In this work, a novel active charge balancing scheme that works with both constant-current mode and constant-voltage mode for monopolar/bipolar/tripolar/quadripolar electrode polarities is proposed. Furthermore, a novel channel circuit and novel channel centric active charge balancer circuit topologies that support both constant-current and constant-voltage stimulation mode in the same structure are developed. Constant-voltage mode stimulation is considered the standard technique of DBS applications for a long time. On the other hand, constant-current mode stimulation is emerging as an alternative solution for DBS applications. Supporting both constant-current mode and constant-voltage mode with active charge balancing makes this work appropriate for DBS applications. The purpose of this work is to increase the flexibility and safety of neurostimulators because this work allows switching stimulation mode after surgery and supplies active charge balancing for both stimulation modes for safety. Neurostimulator ASIC is constructed by 4 channels. Each channel consists of N-Block, P-Block and Channel Centric Active Charge Balancer. Each channel is configurable to supply ground, 10 V, 0-1 mA configurable sink current or 0-1 mA configurable source current in constant-current stimulation mode. Each channel is configurable to supply ground, 10 V, 1-5 V configurable low voltage or 5-9 V configurable high voltage in constant-voltage stimulation mode. N-Block circuit is designed to supply ground, 0-1 mA configurable sink current or 1-5 V configurable low voltage. P-Block circuit is designed to supply 10 V (as VDD), 0-1 mA configurable source current or 5-9 V configurable high voltage. Stimulation period, anodic phase time and interphase delay time are configurable parameters. Cathodic phase duration is not configurable because it is controlled by using outputs of Channel Centric Active Charge Balancer asynchronously. N-Block and P-Block circuits are similar to each other and complementary structures. The supply voltage of the stimulator circuit was chosen as 10 V to prevent headroom problems. Considering high voltage supply requirements, the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 um Bipolar-CMOS-DMOS (BCD) technology process was chosen. Relatively high biasing currents and enable/disable circuits were used for analog blocks to achieve higher performance with lower power consumption. The actual channel current is estimated by using differences of internal currents. Internal currents are mirrored to channel centric active charge balancer circuit to estimate channel current and use it for charge balancing. Timing setting resolution was chosen as 1 us. All analog blocks that are used in N-Block and P-Block were designed in Cadence Virtuoso considering timing, voltage and process constraints. DC, AC, transient and stability simulations were run to verify analog subblocks with Cadence Spectre. Transient simulations were run to verify constant-current stimulation mode and constant-voltage stimulation mode behaviors of N-Block and P-Block. Maximum current error results for constant-current stimulation, maximum voltage error results for constant-voltage stimulation and channel current estimation error results for both stimulation modes are given as simulation results. Channel centric active charge balancer was designed with Cadence environment. Transient simulations were run considering stimulation duration and current amplitude boundaries to verify functionality and determine performance with Cadence Spectre. Charge errors are presented as simulation results. Register Transfer Level (RTL) design of the stimulator controller was designed with Verilog Hardware Description Language (HDL). Synchronous state machines are used to implement the stimulator controller. Asynchronous digital circuits are used to handle outputs of active charge balancer circuits. The stimulator controller was synthesized by using Cadence Genus tool. Place and route process was performed by using Innovus tool. Digital blocks were integrated with analog blocks in Cadence Environment and Analog-Mixed Signal (AMS) simulations were run to verify the behavior of the neurostimulator ASIC for constant-current and constant-voltage stimulation modes with random test vectors. As a conclusion, 4 channel configurable constant-current/voltage mode biphasic implantable neurostimulator ASIC with channel centric active charge balancer was verified by using AMS simulations for both constant-current and constant-voltage stimulation modes. AMS simulation results show that the ASIC works functional and the proposed channel centric active charge balancing scheme is verified for both stimulation modes.
Bandgap reference and low dropout voltage regulator desıgn for capsule endoscopy system

(Graduate School, 2022-06-01) İnam, Benan Beril ; Yelten, Mustafa Berke ; 504191204 ; Electronics Engineering

For the last 40 years, there have been many advancements in biomedical systems as there is a huge demand for them. A capsule endoscopy device is one of the biomedical systems which is used for the imaging of the gastrointestinal system. Endoscopic procedures require two operations because when the procedure starts from the esophagus it can only reach until duodenum, however imaging of the small bowel can be only accessed from the anal cavity. This operation is highly uncomfortable for the patient since the diagnosis of the entire gastrointestinal system requires two endoscopic procedures. To make this operation more comfortable for the patient, capsule endoscopy is developed. The capsule endoscopy system includes a laser source and a laser driver to process the information coming from the source and a transmitter system to transmit the processed data. The transmitter involves an analog to digital converter, transimpedance amplifier, power amplifier, and a phase generator. A single battery is used to supply voltage for all of these mentioned circuits. The battery input voltage of the system decays with time and to increase the lifetime of the capsule it is essential to design a power management unit. This power management unit involves a regulator to create supply voltage for chip blocks and a reference generator to obtain process-voltage-temperature independent reference. For the regulator, a low dropout regulator is chosen as they do not have ripple at the output voltage as in switching regulators which makes them less noisy. Noise is an important parameter because the input signal is low and any input voltage may affect the operation of the circuits. Traditional LDOs require a large off-chip capacitor at the output to create a right half plane zero and stabilize the circuit. However, the capsule is strictly limited in the area hence a cap-less LDO is designed. To enhance the transient performance after removing the output capacitor, a dynamic bias circuitry is added to the design. Output voltage only changes 6 % with process-temperature-voltage corners. Load and line transient results show that even though the input voltage or output load changes with time, the circuit can still regulate the output voltage. To obtain reference voltages for the blocks, a bandgap reference voltage generator is designed. In this design, two different design structures are used to achieve temperature independence. Both MOS and bipolar transistors are employed for this purpose. Design with MOS transistors advantages from operating in the subthreshold region hence supporting lower supply voltages however it has a larger variation at the output due to threshold voltage change over corners. Bipolar transistors benefit from less PVT variation however their performance degrades with lower supply voltages and high temperatures. To use two different characteristics of both designs, a system that switches to better performing structure is built. A comparator is designed to detect temperature and supply voltage. In this system, reference with bipolar transistors operates when the input voltage is higher than 2.8 V and at lower temperatures, and reference with MOS transistors starts to work when the input voltage is lower than 2.8 V and at higher temperatures. To further reduce the variation of the design with MOS trimming structure is implemented to the output resistor and variation decreased from 15% to 5%. The temperature coefficient of the reference generator is calculated as 75C. A power management unit that involves a bandgap reference generator and a low dropout regulator is introduced and designed. Important performance parameters are extracted from the requirements of the capsule endoscopy transmitter. Hence, the layout area is designed to be small and output voltage variation is minimized over PVT corners. The layout of the system is designed and post-layout simulation results are reported in the study.
Design of a microprocessor-based embedded fault diagnostic system and an FPGA-based improvement proposal

(Graduate School, 2022-06-06) Bekar, Onur ; Güneş, Ece Olcay ; 504181292 ; Electronics Engineering

In the past, the use of proprietary hardware, software and protocols in systems and the lack of continuous interaction between the systems /subsystems were a natural obstacle to prevent critical errors from occurring for systems. Therefore, troubleshooting, which has been important in engineering from the past to the present, was not as challenging as in current applications, and the detection of errors was not seen as important part of as it is at present in systems' lifecycle. However, today's applications are complex systems consisting of embedded systems, units, modules etc. that continuously interact with each other, with interfaced, chip to chip, wired and/or wireless communication between. In addition, the widespread use of new technologies, protocols, commercial off-the-shelf (CoTS) products and operating systems has made a remarkable effect to increasing the error's frequency. The increasing complexity of engineering applications has brought challenges associated with the exposure to multifarious failures or errors, affecting the systems' reliability, safety, availability and performability. In this sense, new concepts such as error detection, debugging, error recovery, correction, maintenance and repair over have become indispensable elements of engineering applications. In particular, the detection of errors has become even more important in order to correct the errors, ensure maximum efficiency, and provide optimized and sustainable systems. In this context, the systems, named as Fault Diagnostic Systems; designed specifically for the purpose of detecting and recording the error conditions on the software, hardware or equipment etc. have become widespread in different fields such as, defence industry, industrial control and automation systems, aerospace industry, railway transportation sector, smart factories, electric and hybrid vehicles, power plants, network and information technologies, automotive, medical/healthcare systems and have become an important part of the system design phase. In this thesis, a microprocessor-based embedded fault diagnostic system, which will operate in conformity with or integrated into main units such as control, automation, power units to be used in numerous fields is designed. This diagnostic system is fundamentally a logger system that continuously records sensor data to be sent from the main system and creates the "Error Messages" formed from the waveforms measured by the sensors. The related system is responsible for and able to record the measurements real-timely, operate in different modes according to the present scenarios, detect the data for a certain second before the error occurs in case of a situation that is considered as an "Error" by the main system, and store the error messages permanently in protected memory structures. In the the first chapter of the study, a comprehensive literature review on fault diagnostic systems and embedded systems is made. In relevant parts of the chapter, the related issues are researched in details such as their history, purposes, structures, operating logics, architectures, hardware and software components etc. In the second chapter, a microprocessor-based diagnostic system is designed by starting from the requirements and conceptual system design. Then, it is advanced to Detailed System Design Phase which the system architecture and operating scenario for the system are built and needed specifications such as sampling frequency, data sizes, required memory etc. are calculated. Afterwards, the hardware and software development processes are started respectively by taking the system level designs as reference. In hardware design studies, components used in the Diagnostic PCB such as memory units are selected according to the results of analysis on memory types. In the final part of the hardware design phase, a printed circuit board named Diagnostic PCB is designed in Altium PCB Design Software & Tools by using the recommended information in datasheets, PCB design rules and lessons learnt from past experiences. Then, the PCB is manufactured and verifications tests are performed. Thus, the hardware is verified and software development processes in C programming language are started. In software development process, software architecture is built and the architectural design is made based on the scenario determined in the system design section. The Diagnostic software is designed and verified one by one. In the third chapter, accuracy and performance tests are conducted for the Diagnostic System in the microprocessor-based inverter control unit (ICU) setup, and the results are given. Within the scope of the tests, a dummy traffic is generated and the external systems that Diagnostic System will work with or operate into are simulated. By doing so, real operation scenarios run, and essential optimizations for software are made. Then, the accuracy and performance of the system are retested again and again by simulating the real environment, and the system is verified and validated. The last development within the scope of the thesis is an FPGA-based improvement which is named Multitasking Diagnostic System proposed in the fourth chapter. The related system is developed starting from zero by using VHDL in the VIVADO Design Suite environment as high-level. However, it should be emphasized that no hardware design or tests on physical setup have been made, as in the system developed based on microprocessor. The new system model providing uninterrupted operation is created by considering the advantages of using FPGA for embedded applications such as parallel processing, speed, flexibility, extendibility. In the fifth chapter, accuracy and performance tests are performed also for the Multitasking Diagnostic System through behavioural simulation on the VIVADO Design Suite environment. For all tests, a dummy sensor traffic is generated and a similar scenario is built by taking the scenario followed in the microprocessor-based design processes as reference. Scenarios are run repeatedly by simulating the real environment, and essential optimizations for firmware are made also for. And consequently, the system is also verified and validated. In the last chapter, the microprocessor-based and FPGA-based system designs with their results are summarized, especially the worth-emphasizing parts are given by restating the dissertation main motivation which is the need of an Embedded Diagnostic System. The systems are examined, and a detailed comparison containing their advantages and disadvantages according to the requirements and circumstances is given. Lastly, the contributions to the literature, and the future considerations related to the dissertation is introduced. In conclude, both of the microprocessor-based and FPGA-based systems are successfully designed, verified and validated.
Derin öğrenme ağları kullanılarak doğal ortamda hastalıklı domateslerin belirlenmesi

(Lisansüstü Eğitim Enstitüsü, 2022-06-28) Kapucuoğlu, Köksal ; Kırcı, Mürvet ; 504181277 ; Elektronik Mühendisliği

Birleşmiş Milletler ile Gıda ve Tarım Örgütünün yayımlandığı raporlara göre, 2050 yılında dünya nüfusunun 7 milyardan 10 milyara çıkması beklenmektedir. Bu kurumların yayımladığı diğer bir raporda, 2050 yılında beklenen nüfusu beslemek için önümüzdeki yıllarda dünya genelindeki gıda üretiminin %70 oranında artması beklenmektedir. Kentleşmeden dolayı tarımdaki iş gücünün azalmasından ve geçmişten günümüze kadar gelen geleneksel yöntemlerle gıda üretimin bu kadar arttırılması mümkün olmayacağından tarımda teknolojiden faydalanmak gerekmektedir. Bu anlamda tarım, teknolojik gelişmelerden pozitif anlamda etkilenen en önemli sektördür. Tarımda teknolojik anlamda son dönüşümünü temsil eden tarım 4.0 ile birlikte akıllı tarım ve dijital tarım konuları popüler hale gelmiştir. Akıllı tarımla birlikte gelen otomasyon sistemlerinin en çok uygulandığı alanlardan biri de hasat otomasyonudur. Yetiştirme ve hasat dönemi arasındaki süreyi en verimli şekilde geçirmek, üretilen ürünün kalitesine ve hasat miktarına direkt etki etmektedir. Bu sebeple, yetiştirme ve hasat dönemi arasındaki sürede, hasta bitkilerin tespit edilmesi ve ilaçlanmasının en doğru şekilde yapılması gerekmektedir. Nüfusla birlikte gerekli olan gıda ihtiyacının sürekli arttığı bu ekosistemde, dünyada üretim-tüketim miktarı ve geniş kullanım alanları baz alındığında, domates, en önemli sebzelerin başında gelmektedir. Domates yetiştiriciliği sırasında, yüksek doğruluğa sahip bir hasat otomasyon sisteminden yararlanmak bir gereksinim haline gelmiştir. Geleneksek yöntemlerle domates yetiştiriciliğinde; verilecek gübre miktarı, ilaçlama zamanı ve hasta olan domateslerin tespiti, insana bağımlılığı açısından hataya ve verimsiz bir süreç yönetimine açıktır. Bu yüzden son yıllarda hasat otomasyon sistemlerinde, insan bağımlılığını en aza indiren ve karmaşık sistemlerde bile yüksek doğrulukta ve hızda sınıflandırma yapan derin öğrenme teknolojisinden yararlanılmaktadır. Bu alanda yapılan çalışmaların çoğunda, hazır ortamlarda çekilen domates görüntülerinden oluşan veri kümeleri kullanılmıştır. Bu yüzden yapılan çalışmalar sonucunda sunulan derin öğrenme ağlarından çoğu, saha ortamında çalışmaya uygun değildir. Bahsedilen bu sorunlara karşı bu çalışmada, doğal saha koşullarında da yüksek hızda ve doğrulukla sınıflandırma yapabilen bir sistem önerilmiştir. Son yıllarda yaygın bir şekilde kullanılan derin öğrenme ağları incelenerek performans metrikleri belirlenmiştir. Daha sonra farklı davranıştaki veri kümeleri ile eğitilerek, eğitilen modellerin performansları incelenmiştir. Bu çalışmada; AlexNet, SqueezeNet, MobileNet v1, MobileNet v2, ResNet-50, GoogleNet, Inception v3 ve Inception ResNet v2 ile birlikte toplam 8 farklı derin öğrenme ağı incelenmiştir. Veri kümesi olarak; sınıflandırma çalışmalarında yaygın bir şekilde kullanılan Plantvillage ve Tiny-imagenet veri kümesi ile birlikte bu çalışmada kullanılmak için oluşturulmuş olan Çanakkale domates tarlası veri kümesi kullanılmıştır. Plantvillage veri kümesinde, 9 hastalıklı domates yaprağı sınıfı ve 1 sağlıklı domates yaprağı sınıfı olmak üzere toplam 10 sınıf vardır. Tiny-imagenet veri kümesinde 200 farklı nesne sınıfı bulunmaktadır. Bu çalışmada kullanılması için, Çanakkale-Erenköy'de bir domates tarlasında doğal saha şartlarında çekilen domates görüntülerinden oluşan Çanakkale domates tarlası veri kümesi oluşturulmuştur. Çanakkale domates tarlası veri kümesi oluşturulurken, dahil edilen doğal etkenlere göre bu veri kümesi iki şekilde temsil edilmiştir; temel Çanakkale domates tarlası veri kümesi ve karmaşık Çanakkale domates tarlası veri kümesi. Temel Çanakkale domates tarlası veri kümesindeki her bir görüntü, çekim tekniklerinden ve doğal şartlardan kaynaklanan ışık farklılıkları, görüntü yakınlığı, blur çekim, görüntü çerçevesinde yaprakların olması gibi etkenler içermektedir. Karmaşık Çanakkale domates tarlası veri kümesindeki her bir görüntü ise, temel veri kümesindeki etkenlerin dışında dal, başka bir domates, yaprak gibi ekstra etkenler içermektedir. Bu çalışmada yapılan denemeler sonucunda, Tiny-imagenet veri kümesi ile derin öğrenme ağlarının eğitiminde en iyi sonuca, %42.62 doğrulama doğruluğu ile Inception v3 ağı ile ulaşılmıştır. Plantvillage veri kümesi ile derin öğrenme ağlarının eğitiminde en iyi sonuca, %99.1 ile MobileNet v1 ağı ile ulaşılmıştır. Temel Çanakkale domates tarlası veri kümesi ile derin öğrenme ağlarının eğitiminde en iyi sonuca, %99.78 doğrulama doğruluğu ile Inception ResNet v2 ağı ile ulaşılmıştır. Karmaşık Çanakkale domates tarlası veri kümesi ile derin öğrenme ağlarının eğitiminde en iyi sonuca, %92.92 ile GoogleNet ağı ile ulaşılmıştır. Ayrıca yapılan denemeler sonucunda derin öğrenme ağlarının performans metrikleri incelenmiştir. Bu incelemeye göre; AlexNet, ResNet-50, Inception v3 ve Inception ResNet v2 gibi derin öğrenme ağlarının eğitim maliyeti olarak yüksek eğitim süresine ve model boyutuna sahip olduğunu tespit edilmiştir. Özellikle veri boyutu büyüdükçe, eğitim süresinin de bire bir oranda arttığı belirlenmiştir. Yüksek eğitim maliyetine sahip derin öğrenme ağları arasından en iyi sonuç veren Inception v3 ağının eğitimi; Tiny-imagenet veri kümesi üzerinde 7.5 saat, Plantvillage veri kümesi üzerinde yaklaşık 4 saat, temel Çanakkale veri kümesi üzerinde 5 dakika ve karmaşık Çanakkale veri kümesinde ise 20 dakika sürmüştür. Eğitilen Inception v3 modelinin ortalama model boyutu ise yaklaşık 260 MB'dır. Diğer taraftan SqueezeNet, MobileNet v1, MobileNet v2 ve GoogleNet gibi derin öğrenme ağlarının ise eğitim maliyeti olarak düşük eğitim süresine ve model boyutuna sahip olduğunu tespit edilmiştir. Benzer şekilde veri boyutu büyüdükçe, eğitim süresinin de bire bir oranda arttığı belirlenmiştir. Düşük eğitim maliyetine sahip derin öğrenme ağları arasından en iyi sonuç veren MobileNet v1 ağının eğitimi; Tiny-imagenet veri kümesi üzerinde 75 dakika, Plantvillage veri kümesi üzerinde yaklaşık 2.5 saat, temel Çanakkale veri kümesi üzerinde yaklaşık 3 dakika ve karmaşık Çanakkale veri kümesinde ise yaklaşık 12 dakika sürmüştür. Eğitilen MobileNet v1modelinin ortalama model boyutu ise yaklaşık 27 MB'tır.
3D-printed actuator-based beam-steering approach for improved physical layer security in visible light communication

(Graduate School, 2022-09-05) Erdem, Mehmet Can ; Ferhanoğlu, Onur ; 504201223 ; Electronics Engineering

In this thesis, the design, manufacturing and implementation of a 3D-printed lens scanner-based beam-steering are presented for use in visible light communication (VLC) applications. The scanner, measuring 5 x 5 cm, is designed for low-cost 3D printing with fused deposition modeling using polylactic acid (PLA). The scanning is facilitated through electromagnetic actuation of the lens frame, carrying a conventional 25 mm lens in two nearly orthogonal directions. The serpentine spring that connects the lens frame to the external frame is tailored to offer similar spring constants in the directions of actuation, and minimal (< 1.5 mm) sag due to the mass of the lens. The manufactured actuator was integrated on a miniaturized VLC test-bed (70 cm x 40 cm x 40 cm). Using the test-bed, the applied voltage vs. beam displacement behavior of the actuator was characterized in the lateral plane, and beam-steering on a moving target was demonstrated with face-recognition feedback. The proposed scheme was targeted to offer an improved security measure in VLC through tracking the legitimate receiver (i.e. via face recognition) and using the feedback to steer the focused light onto the targeted device. The joint use of focusing and steering features allows for the legitimate receiver to roam within the room while enjoying the improved secrecy due to focused light. The secrecy capacity for the demonstrated approach was also calculated, which compares favorably to a number of jamming, spatial modulation and beam-forming counterparts. The presented actuator can be used with larger room dimensions, yet up-scaling to larger illumination units will require the use of a lens having a smaller focus to achieve a larger total steering angle. This thesis is composed of five different chapters. The concepts of visible light communication and light fidelity (Li-Fi) are introduced with a thorough literature review in the first chapter, while the techniques used in the thesis are also defined and presented. In the second chapter, the design of the actuator is described through definite computer-aided design (CAD) models and finite element analysis (FEA) simulations, while the experimental setup is also presented. Meanwhile, the demonstrations and the measurement results from the beam-steering operation of the actuator are presented in the third chapter. Then, the discussion section, based on the secrecy improvement through the use of the actuator and the up-scaling of the actuator to real-world dimensions, is presented in the fourth chapter. Finally, the fifth chapter presents the conclusions and further future work based on the actuator. Also, the details regarding the experiments conducted in Chapter 3, some of the designs of the actuator that were changed in order to obtain the final prototype and some discussion based on the mechanical stress on the actuator caused by the weight of the lens are presented in the Appendix section.
FPGA üzerinde 5G uyumlu düşük yoğunluklu eşlik denetim kod çözücü gerçeklenmesi

(Lisansüstü Eğitim Enstitüsü, 2022-09-12) Bilgili, Barış ; Örs Yalçın, Sıddıka Berna ; Pusane, Ali Emre ; 504191203 ; Elektronik Mühendisligi

Günümüzde giderek artan sayısal veri üretimi ve veri ihtiyacı, bu verilerin iletilebilmesi için yüksek hızlı kablosuz haberleşme sistemlerini giderek daha önemli hale getirmektedir. Taşınan veri miktarının artması yeni gereksinimleri de beraberinde getirmektedir. Bunlardan ilki haberleşmenin daha hızlı yapılabilmesidir. İkincisi ise bu verilerin kanaldaki bozulmalardan etkilenmeden alıcı tarafa iletilebilmesidir. Haberleşme insanlar veya makineler arasında gerçekleşse de, hücresel ağlar veya uydu üzerinden sağlansa da yeni gereksinimler eklenebilmesine rağmen bu iki gereksinim değişmemektedir. Bu noktada üretilen standartlar belirtilen gereksinimleri karşılamaya çalışmaktadır. Hücresel haberleşme için güncel bir standart olan 5G'de ileri hata kodlama olarak Düşük Yoğunluklu Eşlik Denetim (Low Density Parity Check - LDPC) kodları veri kanallarındaki bu gereksinimleri karşılamak için önerilmiştir. Uydu haberleşmesinde ise İkinci Nesil Sayısal Video Yayını (Digital Video Broadcasting - DVB S2) gibi standartlarda LDPC kodları kullanılmaktadır. LDPC kodları yapıları itibariyle esnek tasarım ve uygulamalara uygun kodlardır. Farklı blok boylarında ve paralel çalışmaya elverişli oldukları için Alanda Programlanabilir Kapı Dizileri (Field Programmable Gate Array - FPGA) ile gerçeklenmeleri avantajlı bir hale gelmektedir. LDPC kodları farklı kod çözme algoritmalarıyla çalışabildikleri için FPGA gerçeklemeleri yapılmadan önce bu algoritmalar performans ve gerçeklemeye uygunluk açısından incelenmelidir. Kod çözücünün düşük alan kullanımına ve yüksek veri hacmine sahip olması gerektiği için buna uygun bir algoritma seçilmelidir. LDPC kodları genellikle bir eşlik denetim matrisi ile tanımlanırlar. Kod çözücü tasarımında bu matris, veri depolama birimlerinin boyutlarını ve bağlantıları belirler. Kod çözücüde algoritmanın çalıştığı asıl birim ise Denetim Düğümü Birimi ( Check Node Unit - CNU) olarak tanımlanır. Bu çalışmada 5G Yeni Radyo (5G New Radio - 5G NR) standardı temel alındığı için veri boyutları ve bağlantıları büyük oranda belirlidir. Algoritma seçimi, paralelleştirme ve veri hacmini arttırma üzerine çalışmalar yapılmıştır. Donanım gerçeklemesi yapılırken karşılaşılan veri depolama, adresleme ve sıralama sorunlarına çözümler üretilmeye çalışılmıştır. Döngüde FPGA (FPGA in the Loop - FIL), FPGA'de çalışması için bir donanım tanımlama diliyle (Hardware Description Language - HDL) yazılmış kodları MATLAB ortamı ile entegre ederek gerçek donanım üstünde çalışan kod ile yazılımdaki kodların beraber benzetiminin yapılması sağlayan doğrulama programıdır. HDL ile tasarım yaparken doğrulama yapmak çok önemli bir yer tutmaktadır ve FIL kullanılmadığı durumda herhangi bir bloğun doğrulamasını yapmak için test dosyaları oluşturup veri grupları hazırlayarak benzetim yapılması gerekmektedir. FIL sayesinde MATLAB ortamında oluşturulan veriler örnek modelle aynı anda gerçek donanım üzerinde çalışan HDL koduyla kıyaslanarak sonuçları doğrulanabilmektedir. 5G NR standardındaki LDPC matrisleri farklı boyutlara ve farklı satır ağırlıklarına sahip oldukları için bu çalışmada tasarlanan LDPC eşlik denetim biriminin farklı sayıda giriş ile çalışabilmesi gerekmektedir. Bu nedenle FIL kullanılarak farklı sayıda girişler için MATLAB ortamında doğrulama yapılmış ve FPGA üzerinde çalıştırılarak test edilmiştir. Bu çalışmada hem FIL ile doğrulama yaparak tasarım ve doğrulama süreçlerinin hızlandırılması, hem de donanıma uygun algoritmalar seçilerek karmaşıklığı düşük ve veri hacmi yüksek bir eşlik denetim birimi tasarlanması, eşlik denetim biriminin çalışmasına örnek göstermek amacıyla 5G NR standardına uygun bir üst seviye tasarımının yapılması amaçlanmıştır.
Multiplication circuit block design using reversible logic gates

(Graduate School, 2022-09-23) Gönül, Berkay ; Güneş, Ece Olcay ; 504181204 ; Electronics Engineering

There has been an ever-increasing demand for electronic devices and computers since the day they were first produced. This request can be examined under three main headings; faster, cheaper and smaller. Over the years, there has always been upgradings on the smaller production technologies. This upgrades create chances to produce smaller applications to meet the demand on this area. Also, for a microchip, being smaller means having shorter lines between circuits, smaller serial resistances on circuits, closer transistors inside the chip etc. These features create a positive momentum for being faster. Because, smaller chip means that more resources can fit inside it which leads to parallel computing and shorthens logic operation delays. Also, smaller designs require less power to operate and loss less energy during computing. So being smaller affect both speed and energy in a positive way. However, Moore's law [1] says that smaller chip technologies will saturate eventually. This is because technology and physical limits. Even if smaller technologies would be produced, there is a physical barrier which is the diameter of electrons. In today's computing devices, electrons move from higher potentials to lower potentials to change states of bits. These bit changes occur in a small transistors. Even if incredibly small transistors would be produces, at one point, channel widths of transistor will be a limit for enough electron flow. If electron flow gets slower, state changes become slower so this directly affects the speed demand. In such cases, there can be alternative solutions such as using multi-core applications. Neverthless, once the core sizes and numbers are increased, delays and power consumptions are negatively affected. One other way to overcome faster applications without these limits is using and developing quantum computing devices. These devices work different than today's computers. They use quantum bits in other words qubit which can be 0 and 1 at the same time where classical computing devices uses 0 or 1 as a state. Since the possibility of states increase, the faster applications can be designed. This infastructure is based on quantum physics. Thus, quantum computers can solve more complex problems and run complex simulations faster than classical computing devices. There are some requirements to develop such devices, for example, these devices need to be isolated from enviromental affects or noises. They are difficult to built. They are developed for special tasks rather than being multi task computers. Also, they need to be build reversible since the creation of quantum states can not be erased. On the other hand, reversible design create less power loss opportunity because in reversible computing there is no need to erase or overwrite a bit. Every erase and write operations creates energy loss by heat around 3 x 10−21 Joule at room temperature. In this situation, using reversible gates can create optimizations for the designs. This study is mainly focused on this research area. So, reversible logic gates mean that n to n mapped, universal gates which leads finding it's unique inputs using it's outputs. Here, universal word means that using the same gate can help to find it's own unique inputs. So, learning universal gates, their application areas, advantages/disadvantages are studied along this thesis and one example is performed to realize their usage in an application. This application is chosen to be a multiplication circuit block example because, multiplication circuit blocks are one of the most resource and time demanding blocks in digital systems. So, using reversible logic gates in a multiplication circuit block example would be helpful to both understand the gates and having a design approach for a widely used application in the literature. The main motivation during the design is to use one single gate type to perform less circuit complexity and fast development opportunity.
Range profile extraction in noise radars based on the target characteristics

(Graduate School, 2023) Çaha Karabağ, Şevval ; Selçuk Paker ; 777760 ; Elektronik-Haberleşme Eğitimi Ana Bilim Dalı

Continuous and pulsed radar systems are frequently used in military and civilian applications. The detection capability of a radar depends on the antenna properties used, the size and material properties of the target to be detected, the noise level of the receiving antenna and the RF line, and the effective output power of the radar, which is one of the most important. The effective output power of radar systems increases in direct proportion to the pulse width, thus improving the signal-to-noise ratio (SNR). A high SNR level improves detection performance and measurement accuracy. However, in conventional pulse radar, increasing the pulse length causes a decrease in the range resolution, which is undesirable. Different types of pulse compression are used to achieve high output power and low range resolution. These include frequency modulation and phase modulation. One of the most popular frequency modulations is the pulse compression technique based on linear frequency modulation. In phase modulation, which is another method, the phase of the radar pulse can be generated by different intrapulse modulations such as binary phase modulation, poly-phase modulation, and noise or pseudo-noise modulations. Phase-modulated waveforms are obtained by dividing a pulse into multiple sub-pulses to achieve the required main lobe and side lobe levels. The length of a single sub-pulse obtained defines the radar's range resolution.
Design and implementation of an 11-bit 50 ms/s flash-assisted successive approximation register ADC

(Graduate School, 2023) Maden, Fatih ; Karalar, Tufan Coşkun ; 783612 ; Electronics Engineering Programme

Modern electronic systems transmit, store, and process data. Pure analog solutions are no longer practical due to the increasing complexity of electronic systems. Thanks to advances in digital signal processing (DSP), signal processing and storage have moved from analog to digital domains. However, first of all, analog signals should be converted to digital signal in order to take advantages of DSP. Therefore, DSP systems are needed ADC. There are different ADC topologies in the literature because each system has different performance requirement. The most popular ADC architectures are flash, pipeline, SAR, delta-sigma and time-interleaved ADCs. Each of these architecture has own advantages and disadvantages in terms of resolution, sample rate etc. SAR ADC has been one of the most widely used ADC architectures over the past decade. Due to its largely digital structure, SAR ADC take advantage from CMOS technology scaling. SAR ADCs are generally preferred for medium accuracy, medium speed, and low power applications like biosensors, image sensors, and wearable devices because they have the highest energy efficiency of all moderate bandwidth, moderate resolution converters. However, resolution and speed of the SAR ADC is restricted by comparator offset and mismatch in the DAC. Therefore, many calibration and redundancy techniques have been proposed to improve SAR ADC resolution, but they increase design complexity and don't solve bandwidth issues. In this work a new method proposed in order to increase resolution of the SAR ADC without speed degradation. 11-bit flash assisted SAR ADC with a 50 Msps date rate designed and simulated in TSMC 65nm technology node. The working principle of the our design is similar to pipeline ADC. Conversion is completed in two cycles . In the first cycle SAR ADC sample the input signal and generate the most significant eight bit. In the second cycle, the residue voltage produced by the SAR ADC is amplified through the switch capacitor circuit and converted into three bits with the help of the flash ADC. Then output of the SAR ADC and flash ADC is aligned and 11-bit resolution is obtained. The thesis consists of five chapters, with the first chapter introducing the work and objectives. In the second chapter, background information about ADC design and commonly used ADC architectures are reviewed. In the third chapter, the architecture of the designed flash-assisted SAR ADC is explained. In chapter four, simulation results for the designed blocks are presented and interpreted. The thesis is concluded and compared with similar work in the fifth chapter.
Elektronik kalkan için parazitik parametrelerin çıkarımı

(Lisansüstü Eğitim Enstitüsü, 2023) Meral, İmran ; Yalçın, Müştak E. ; 806658 ; Elektronik Mühendisliği Bilim Dalı

Bu çalışmada, tümdevreleri istilacı (invasive) saldırılara karşı koruma amaçlı kullanılan kalkana ilişkin metal hatların parazitik parametrelerinin çıkarımı çalışılmıştır. VLSI (çok büyük ölçekli tümdevre) devrelerinde, özellikle yüksek frekanslı sayısal devrelerde, devreler arasında bağlantıyı sağlayan metal hatlara ilişkin parazitik etkilerin, devrelerin çalışma performansı üzerinde etkisi mevcuttur. Devrenin doğruluğunun ve performansının sağlanması için olası bütün parazitik etkilerin modellenmesi ve tasarım aşamasında kullanılması önem arz etmektedir. Bu çalışmada da tümdevreyi istilacı saldırılara karşı korumak amacıyla tasarımı yapılacak kalkanın metal hatlarına ilişkin parazitik etkiler göz önüne alınarak kalkan tasarımcısına yardımcı olacak bir yazılım geliştirilmesi hedeflenmektedir. Gelişen teknolojiyle birlikte finans, sağlık, askeri ve bu gibi güvenlik açısından kritik öneme sahip sistemlerin de dijitalleşmesi artmaktadır. Yaygın kullanım alanlarına sahip ve insanlar için kritik öneme sahip dijital sistemlerin kötü niyetli kullanıcılardan korunması önemlidir. Saldırganlar, kişisel gizli verilere ulaşmak için saldırı yöntemleri geliştirmişlerdir. Yapılan saldırılar geniş bir çeşitliliğe sahiptir. Çiplere yapılan saldırılar istilacı saldırı (invasive attack) ve istilacı olmayan saldırı (non-invasive attack) olarak ikiye ayrılmaktadır. İstilacı saldırı çeşidinde, saldırganlar çip paketine doğrudan erişmektedir. Saldırganlar çipin paketini açarak yongaya (die) erişebilmekte ve yonga üzerindeki tümdevreden ölçüm alabilmektedir. Yonganın çip paketinden çıkartılması kimyasal işlemlerin yapılmasını gerektirmektedir. Kimyasal bir süreçten geçirilen çipin üst katmanı açılır ve kritik öneme sahip bilgileri saklayan devre yapısına ulaşılabilir. Yerleşim düzeninin yeniden çıkarılmasında amaç devre yerleşim düzenini yeniden elde etmektir. Saldırganlar CCD kameralı bir optik mikroskop yardımı ile yonganın her katmanının yüksek çözünürlüklü görüntüsünü elde etmektedir. Programlar aracılığıyla gözlenebilen katmanları da kaldırılabilmektedir. Saldırgan devredeki ROM, RAM, EEPROM, ALU ve komut kod çözücüsünden geçen metal hatları inceleyebilir. Mikro-problama (micro-probing) tekniği istilacı saldırılar için önemli bir yöntemdir. Mikro-problama tekniğinde çipin paketi çıkarılmaktadır. Bu saldırı türünü gerçekleştirmek için özel laboratuvarlarda uzun bir süreye ihtiyaç vardır. Yonga üzerinde şifreleme işleminin yapıldığı bölge açılarak ya da problama (probing) yapılarak şifreleme işlemine ilişkin anahtarlar bellek elemanları üzerinden okunabilir ya da şifreleme işlemine ilişkin devre çalışırken ölçüm alınarak saldırı gerçekleşebilmektedir. Odaklanmış iyon ışını (FIB) tekniğinde yonga üzerindeki bağlantılar değiştirilebilir ve yonga üzerindeki tüm devre araştırılabilir. FIB cihazı ile yonganın metal katmanındaki yollar kesilebilir ve yeni yollar veya izolasyon katmanları oluşturulabilir, silikon alanının katkısını değiştirmek için iyonlar yerleştirebilir, çipin en alt katmanındaki iletken yapılara yeni geçişler oluşturabilir. İstilacı olmayan saldırı çeşidinde saldırıya uğrayan çip fiziksel olarak bir zarar görmemektedir. Saldırıda kullanılan düzenek normal kart okuyucusu gibi görünebilmektedir. İstilacı olmayan saldırı türü bazı uygulamalarda iki nedenden dolayı tehlikeli olabilmektedir. Birincisi, güvenliği ihlal edilmiş kartın sahibi, gizli anahtarın çalındığını fark etmeyebilir.
İnsansız hava araçlarında gömülü yapay zeka tabanlı görüntü eşleştirme yöntemi ve uygulaması

(Lisansüstü Eğitim Enstitüsü, 2023) Öksüz, Engin ; Akgül, Tankut ; 817014 ; Elektronik Mühendisliği Bilim Dalı

İnsansız Hava Araçları (İHA) günümüzde fotoğraf, gözetleme, haritalama ve araştırma amaçlı olarak yaygın bir şekilde kullanılmaktadır. Bir İHA'nın hava görevlerini sorunsuz bir şekilde yerine getirebilmesinin ön koşulu, kendi konumunun doğru bir şekilde konumlandırılmasıdır. Geleneksel İHA navigasyonu, konumlandırma için Küresel Navigasyon Uydu Sistemine (GNSS) dayanır; ancak bu sistem istikrarsızlık ve girişime yatkınlık gibi dezavantajlara sahiptir. İHA uygulamalarının hem endüstriyel hem de araştırma senaryolarında hızlanan gelişimi göz önüne alındığında, bu hava sistemlerinin, görüntü tabanlı yöntemlerle şehir içi veya kırsal ortamlarda yerelleştirilmesi ihtiyacı da artmaktadır. Bu tez çalışması kapsamında bir İHA'nın coğrafi koordinatlarını hesaplamak için derin öğrenme tabanlı özelliklerden yararlanan görsel tabanlı bir konumlandırma algoritması geliştirilmiş ve çalışması yapılmıştır.
Yüksek hızlı baskı devre kartlarında sinyal bütünlüğünün incelenmesi

(Lisansüstü Eğitim Enstitüsü, 2023) Pehlivan, Kübra Açelya ; Yelten, Mustafa Berke ; 782513 ; Elektronik Mühendisliği Bilim Dalı

Modern elektronik cihazlarda sinyal hızlarının oldukça artması ile yüksek hızlı iletim hatlarının olduğu PCBlerin tasarımı daha çok dikkat gerektiren hale gelmiştir. Dijital haberleşme sistemlerinde sinyal bütünlüğü ve elektromanyetik uyumluluğun sağlanması daha da önem kazanmıştır. Bu PCBlerin tasarımında farklı tasarım teknikleri ve parametreleri kullanılması gerekmektedir. Yüksek hızlı iletim hatları çizilirken bu tasarım parametrelerine dikkat edilmesi gerekmekte, aksi durumda kartta sinyal kayıpları ve hataları oluşabilmektedir. Aynı zamanda bu PCBlerin doğru bir şekilde analiz edilmesi ve simüle edilmeleri, sinyal bütünlüğünün sağlanması ile oluşabilecek hataların önceden görülebilmesini ve düzeltilebilmesini, ayrıca üretim maliyetinin düşürülmesini sağlar. Sinyal bütünlüğü problemleri, yansıma ve iletim kayıpları kaynaklı sinyal zayıflaması ve sinyaller arasında oluşan çapraz karışma kaynaklıdır. Bu problemleri en aza indirmede değişik tasarım parametreleri ve yaklaşımları etkili olmaktadır. Bu parametreler PCB için stack-up, yerleşim, iletim hattının geometrisi, kullanılan bağlantı ve terminasyon elemanları olarak belirtilebilir. Bu tez kapsamında yukarıda açıklanan tasarım parametreleri ve sinyal bütünlüğü konusu literatür araştırması yapılarak kapsamlı olarak ele alınmıştır. Daha sonra bu parametrelerden bazıları belirlenerek simülasyonlar gerçekleştirilmiş ve bu parametrelerin iletim hattının sinyal bütünlüğü üzerindeki etkileri incelenmiş ve yüksek hızlı iletim hatlarının bulunduğu PCBler için bir tasarım modeli oluşturmak hedeflenmiştir. Kullanılan parametreler stack-up ve malzeme seçimi, seri komponentlerin etkisi, via türü ve yapısıdır. Simülasyonlarda çok katlı PCB'lerde sinyal bütünlüğü için önemli bir tasarım parametresi olan vialar üzerinde yoğunlaşılmıştır. Via geometrisinin sinyal bütünlüğüne etkisi via ped çapı, delik çapı, diferansiyel vialarda vialar arası mesafe, antiped çapı, paylaşımlı via anti-ped yapısı, fonksiyonel olmayan via pedleri, via yüksekliği ve via kalıntıları çerçevesinde incelenmiştir. Bu parametreler ile sinyal bütünlüğü sonuçları karakteristik empedans ölçümü, yansıma ve iletim kayıpları kapsamında karşılaştırılmıştır ve bu parametrelerin sinyal bütünlüğü üzerindeki etkisi gösterilmiştir. Simülasyon sayıları artırılarak bu parametrelerden hangilerinin sinyal bütünlüğüne daha baskın olarak etki ettiği ve via optimizasyonu için nasıl bir yol izlenebileceği araştırılmıştır. Aynı zamanda teorik olarak bilinen etkilerin seviyesi simülasyon ile belirlenerek fayda-zarar analizinin yapılmasının kolaylaştırılması amaçlanmıştır. Karakteristik empedansın hesaplanması ve stack-up oluşturulması için Saturn PCB Design ve Advanced Design System (ADS) programları kullanılmıştır. Hatların şematik ve PCB çizimleri için Altium Designer Programı, simülasyonlar için ise 3 boyutlu tam dalga elektromanyetik alan simülatörü eklentisi bulunan ADS programı kullanılmıştır.
Investigation of microstructure movement under flow by using image processing and deep learning

(Graduate School, 2023) Khosroshahi Sarbazzadeh, Saeed ; Erten, Ahmet Can ; 883275 ; Electronics Engineering Programme

In many industrial and biological applications, the viscosity of chemical and biological fluids is a crucial material property that needs to be precisely measured A variety of techniques has been developed to measure viscosity. The micropillar-based microfluidic viscometer method uses viscosity and flow-induced micropillar displacement. Before making general viscosity measurements, calibration curves (viscosity vs. micropillar tip displacement) are created using solutions with known viscosities. Filming experiments with glycerol/water solutions with viscosities ranging from 2 to 100 cP at fixed flow (shear) rates are done to achieve this. The experiment is then repeated using a fluid sample whose viscosity is determined. In captured experiment videos with the sample fluid, the displacement of pillars is measured for this purpose using ImageJ, an image processing program. The measured displacements are then mapped to the calibration curves to determine the sample fluid's viscosity. Results obtained using this method are precise. The disadvantage is that using ImageJ to calculate displacement takes time and requires manual work. Therefore, in this study, we used two distinct image processing algorithms that yield results much more quickly. These are Lucas-Kanade (KLT), and Hough Circle, which are used in classical video processing, and the FlowNet2 neural network model. The KLT algorithm is a popular differential technique for estimating optical flow. We tracked the four corners of the pillar tip using the KLT to determine the displacement of the pillars. The final displacement data was then determined by averaging these four corner displacements. Contrarily, the convolutional neural network (CNN) Flownet2 is employed in deep learning to interpret visual images. Huge displacement control and precise estimation of minute details in the optical flow field are two features of FlowNet2. We made use of the pre-trained FlowNet2 model on the THINGS dataset. We used the first frame of the video as the model's first entry and the frames that came after that as its second entry to find out about displacement. We used ImageJ data as a reference to determine the methods' accuracy when determining the accuracy of the suggested methods for 10 videos. Regarding ImageJ, KLT, Hough Circle and FlowNet2 provided an average accuracy of 95.45%, 91.47%, and 95.62%, respectively. We saved a lot of time by using these techniques because we didn't need human assistance. With KLT, we were able to generate viscosity results 158 times faster with respect to ImageJ, with Hough Circle 396 times faster and with FlowNet2 10 times faster.

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Çıkarma tarihi ile LEE- Elektronik Mühendisliği-Yüksek Lisans'a göz atma

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