LEE- Elektronik Mühendisliği-Yüksek Lisans
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ÖgeMulti-purpose reconfigurable impedance matching network designs and antenna applications(Graduate School, 2024)Modern radio frequency communication front-ends utilize multiple parallel and cascaded transceivers to accommodate new communication standards that require additional frequency band allocations. However, the utilization of more and more transceiver modules to accommodate emerging communication standards results in higher costs, additional power consumption, larger circuit board sizes, and an increased probability of failure. Reconfigurable radio frequency circuits have become a promising solution to eliminate the deployment of multiple transceivers. A reconfigurable transceiver can cover multi-ple communication standards by changing its operational frequency that conventional front-ends require numerous transceivers. Also, reconfigurable transceivers can be configured with new communication standards without necessitating new transceiver designs. The use of reconfigurable circuit designs is not only advantageous in terms of reducing costs, board sizes, and enabling versatility in the utilization of new standards but also performance deviations caused by external effects and damaged parts of the circuits can be compensated. Owing to the mentioned advantages, interest in reconfigurable circuits has increased gradually both in academia and industry. The replacement of conventional circuits with reconfigurable versions has been studied in literature and basic implementations have been utilized by the industry over the years. One of these circuits which is used in all front-ends is impedance matching networks. Since impedance matching networks are at the core of all radio frequency and microwave circuit designs, reconfigurable versions have to be deeply investigated. In this thesis, novel frequency and load-tunable multi-purpose reconfigurable impedance matching network designs are proposed by starting from their building blocks and designed networks are evaluated in terms of various performance metrics. Microstrip transmission lines that are used in the reconfigurable impedance matching networks are simulated and measured first. Electromagnetic (EM) simulations and measurements are in good agreement and indicate less than 0.5 dB insertion loss with less than 1% signal power reflection inside the 0.1 GHz-4.5 GHz frequency band. Since the reconfigurable networks include tuning elements that have to be properly controlled without introducing additional power loss, a DC bias network is designed and examined. The bias network includes a DC blocking capacitor, two decoupling capacitors, and an RF choke inductor. Component values are calculated by considering operational frequency. Schematic, EM Co-simulations, and measurements revealed that insertion loss of the bias network is less than 0.25 dB with -20 dB return loss at the input and -30 dB isolation at the DC port. Also, the designed bias network achieves complete DC blocking performance under 8 V which is the control voltage limit of the tuning components. In this way, tunable circuit elements that are sensitive to DC voltage change can be controlled independently from each other. As a final building block, hyperabrupt varactor diodes are examined with analytical calculations, simulations, and measurements. Since hyper-abrupt varactor diodes are more sensitive to DC bias voltage than conventional abrupt varactor diodes, their equivalent circuit models are less accurate. In order to construct a more accurate measurement-based model, first, the low-frequency response of the varactor diodes is examined. The grading factor and capacitive tuning ratio of the varactor diode are corrected according to measurement results. High frequency response of the varactor diode demonstrates self resonance frequency which is used for revision of package parasitics. Finally, the varactor diode’s Q-factor and insertion loss are obtained to evaluate applicability on the desired multi-purpose reconfigurable impedance matching network. The Q-factor of the varactor diode increases with the applied reverse bias voltages and reaches to 1100 at 50 MHz. Insertion loss is less than 0.35 dB between 0.1 GHz and 5 GHz. Both the Q-factor and insertion measurements reveal that the selected varactor diode suits expectations on the tuning element well. After examining building blocks, and constructing measurement-based circuit models, a reconfigurable impedance matching network is analytically synthesized with and without including varactor diode parasitics. The initial design is then modified to reach a better Q-factor which includes fewer components on the series branch of the circuit. A modified design is also synthesized with and without parasitic injection. First, designed matching networks are examined in terms of insertion loss with schematic, EM Co-simulations, and measurements. Schematic simulations provide better estimation for measurement results in initial designs whereas EM Co-simulations are in better agreement with measurements for modified designs. The initial and modified designs with parasitic injection have less than 1.5 dB insertion loss and less than 2.5 dB insertion loss without parasitic injection inside the operational frequency band. Then evaluations are continued with the Q-factor which is the key indicator of broad Smith-chart impedance coverage. EM Co-simulations show better performance in terms of estimating measurement results compared to schematic simulations. Measurement results demonstrate Q-factor of the parasitic injected designs have a higher Q-factor than those without parasitic injection. This reveals that proper circuit synthesis is more important than reducing the number of components in series branches to obtain a higher Q-factor. However, reducing components in series branches still contributes to obtaining a higher Q-factor. The highest Q-factor is obtained on the modified design with parasitic injection with 70. The nonlinear behavior of impedance matching networks is also evaluated by determining output 1-dB compression points. A measurement set-up is constructed by using a preamplifier and the output of the amplifier is connected to matching networks. Measured results reveal that initial designs have almost the same 1-dB output compression point around 24.5±0.2 dBm, where the modified design with parasitic injection reaches the highest with 25.8 dBm and without parasitic injection has the lowest value with 23.5 dBm. Finally, Smith-chart impedance coverage of each matching network is examined with simulations and measurements. In order to measure the impedance coverage, an algorithm is proposed that measures the input impedance of matching networks under every possible combination of varactor diode reverse bias voltage from 0 V to 8 V with 0.2 V steps. Schematic simulations are in better agreement with the measurement results. Q-factor measurement results are aligned with the Smith-chart coverage which verifies the design concerns. The highest impedance coverage is obtained with the parasitic injected modified design which provides at least 50 % impedance coverage between 0.9 GHz and 2.2 GHz. Comparison with similar works reveals that the designed reconfigurable impedance matching network has superior performance in terms of frequency tunability, nonlinearity, insertion loss, and noise figure. This improvement is achieved by using a proper circuit model for enhanced tuning elements and detailed circuit synthesis. The modified design with parasitic injection which has the best performance among the other designs is used in antenna mismatch compensation. A simple patch antenna matched to 50Ω is simulated and measured in free space. Then, in proximity to the human head, the change in the input impedance of the antenna is observed with simulations and measurements. When the antenna is close to the human head, the input impedance is no longer matched to 50Ω. In that case, the transceiver has to consume more power to ensure communication. However, with the help of the designed matching network, input impedance change is compensated by tuning the input impedance to 50Ω for efficient power transmission. Moreover, a center frequency tuning feature is provided to the antenna with the help of the designed reconfigurable impedance matching network.
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ÖgeImplementation of a super-resolution algorithm using model composer(Graduate School, 2023)Today, the advancement of technology has multifaceted effects. The effects of these advancements can be given as examples of the increase in resolution and detail in the vision sensor systems at the front end, the developments in hardware and integrated technologies at the middle level, and, in the back end, the innovations in the implementation and testing stages of the compilers that program these hardware and integrations. Especially in the last ten years, developments in internet and image compression algorithms and devices such as televisions, smart phones and computers with image playback capability have increased the features such as the resolution and detail in the image. Although these developments can be followed by current cameras and image detection devices produced today, it is obvious that the resolution of the videos and photos recorded in the past should be increased. Meanwhile, basic and simple mathematical convergence solutions such as bilinear and bicubic interpolation are frequently used. However, these algorithms do not have the ability to increase information such as continuity, detail and sharpness in images with the weighted averaging basis they use. For this reason, special solutions aiming to increase the mentioned features have been produced. These solutions are called super-resolution imaging. Field Programmable Gate Arrays (FPGAs), which allow experimentation during prototyping and algorithm development with their ability to be reconfigured with hardware improvements, have also become useful for the implementation of algorithms with large dimensions and high computational needs. Although the development of the configuration files for these ICs is primarily done through IDEs that convert HDL codes to bitstreams, background compiler developments have also accelerated. Vivado High Level Synthesize compilers based on C/C++ programming languages have been used since 2014. The Model Composer extension, which is based on this compiler and provides FPGA implementation on MATLAB Simulink, has also accelerated the validation and development processes. This study aimed to use these three parts together and aimed to develop the underlying algorithm. Meanwhile, it aims to provide readers with the opportunity to observe how effective and functional the Model Composer is during validation and validation.
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ÖgeSurface acoustic wave resonator characterization for gas and liquid detection(Graduate School, 2024-07-12)Surface Acoustic Wave (SAW) resonators have garnered significant interest in recent years due to their advantageous properties, including high Q-factor, low power consumption, and compact size, making them ideal candidates for various sensor applications. SAW resonators can be used as material detection devices since manipulations to the substrate along the delay line can alter the characteristics of the device. The objective of the study is to determine the characteristics of a SAW resonator based network when it is exposed to gasses and liquids for sensor applications. Several versions of PCBs are manufactured for the resonator measurements. These PCBs are customized according to the shape of the resonator. Some of the PCBs are then further customized to incorporate multiple signal lines from the same resonator with the help of switches. Resonators are wire bonded in order to connect them to PCBs thus reducing the chances of damaging during measurements. Wire bonding process was optimized through experimentation with already damaged wafers or test wafers. Through the use of a Vector Network Analyzer (VNA), S parameter information were obtained under different conditions for various resonators. Firsly VNAs were calibrated for desired frequency range and parasitic cable effects were removed. Measurements for resonators were taken as a baseline with just the bondwires and the PCB. Same measurements were repeated in a Faraday cage with lights turned off to see the effects of light and noise on the resonator. Resonators were then coated with 2 different sensing materials Phthalocyanine and Polyvinylpyrrolidone (PVP). After coating the resonators same measurements were repeated on both bandpass and bandstop filtering behavior resonators to acquire data. Acquired data were then used to create a model filter then simulated with Colpitts Oscillator configuration to see frequency selectivity. The results showed that noise and light effects were minimal on the resonators since data from Faraday cage and baseline measurements were almost identical. It was observed that even coating resonators with a sensing material changed the behavior of the resonator within the ranges of the kilohertz. Additionally, since PVP also interacts with moisture, the effectiveness of the coating was observed by blowing on to the resonator and observing frequency shifts.
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ÖgeArtificial neural network based electrical machine fault classification on FPGA(Graduate School, 2024-12-17)Electrical machines and drives play a critical role in modern society, spanning industrial equipment to renewable energy production. The reliability and efficiency of these systems depend on continuous performance monitoring and the early detection of potential issues. Condition monitoring systems are essential for evaluating the performance of machines and detecting potential faults early, thereby reducing unexpected downtimes and maintenance costs. Traditional fault detection methods include vibration analysis, thermography, and oil analysis. Vibration analysis is used to identify mechanical issues, while thermography can detect overheating that may indicate electrical or mechanical problems. The integration of artificial intelligence (AI) and machine learning techniques has significantly enhanced fault detection capabilities. AI techniques such as artificial neural networks (ANN) and support vector machines (SVM) can process large datasets to predict potential faults in advance. This thesis aims to develop and implement an ANN-based fault diagnosis system for electrical machines on an FPGA platform. The system will leverage the high-speed processing and parallel computing capabilities of FPGAs to achieve real-time fault detection and diagnosis. Additionally, this method will be tested with different datasets to evaluate its generalizability. The thesis comprises two main sections: deep learning and FPGA applications. The first section describes the dataset used, data processing, and the development of the CNN architecture. The second section discusses the implementation of the CNN model on FPGA using VHDL. Experimental results are presented in the final section. In the deep learning section, a CNN-based fault detection model has been developed for ensuring the reliable operation of electrical machines. The dataset used consists of vibration signals obtained from the MAFAULDA database. The data were used to train and test the CNN model, with performance evaluated based on accuracy, precision, recall, and F1 score. The ability of CNNs to learn local patterns and features makes them particularly effective for fault detection. The FPGA application section covers the implementation of the CNN-based fault detection system on FPGA. Convolution_1D, Convolution_1D_Middle, Convolution_1D_No_MP, and Dense layers were developed using VHDL. Real-time fault detection was performed using the Nexys A7 development board. The parallel processing capabilities of the FPGA allowed for high-speed computations, making the system suitable for real-time applications. This implementation efficiently handles large volumes of data, ensures low latency, and maintains high accuracy. When developing a CNN-based fault detection system using VHDL, optimizing the layers and processes is crucial. The Convolution_1D, Convolution_1D_No_MP, and xx Convolution_1D_Middle layers perform 1D convolution operations on the input data using predefined kernels. The Convolution_1D layer extracts fundamental features from raw sensor data, while the Convolution_1D_No_MP layer maintains higher resolution for detailed analysis. The Convolution_1D_Middle layer further refines the features, ensuring high accuracy in fault detection. The Dense layer processes these features into the final classification result. The TOP_CNN module integrates all layers, managing the data flow and producing the final fault classification result. In conclusion, a CNN-based fault detection system has been developed and implemented on FPGA. The system significantly enhances the reliability and efficiency of electrical machines. Future research will involve testing this method with broader datasets and different application areas to further evaluate and improve its effectiveness. This work contributes to the implementation of proactive maintenance strategies in industrial processes, ensuring operational excellence of machinery
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ÖgeCommunication range extending PSK backscatter modulation in passive RFID(Graduate School, 2024-02-05)In this study, analyses and simulations to increase the communication distance of passive RFID systems in forward and reverse directions have been carried out through equations. All modulation techniques have been compared fairly with the equations obtained by classical circuit theory and based on the power of the RFID tag and reader. It has been shown that the time at which the average peak power consumption of the tag occurs during communication affects the communication distances. After using the parameters determined by the regulatory institutions and obtained from the literature, the free parameters on the system were obtained by keeping any parameter constant, and thus concrete data was obtained. The results were further confirmed using data from recent studies found in the literature with tag threshold power between 664 nW and 1 μW. It was concluded that the performance of binary phase shift keying modulation is better than amplitude shift modulation in terms of communication distance, signal-to-noise ratio or bit error rate, and receiving antenna gain. Long communication distance is important in environments where there are many obstacles and noise, as it enables the tag to work successfully. The long communication distance feature can be transformed into a receiving antenna that can be used in smaller sizes and at less cost. Similarly, it also provides more reliable communication with a higher signal to noise ratio or less bit error rate at the receiving end. It has now been observed that the communication distance of RFID systems has begun to be limited by backward communication rather than forward communication, which provides energy and information. This situation shows that it will be necessary to switch to a bistatic antenna configuration for the reader instead of a monostatic antenna configuration. Equations have been put forward that the reader configuration change is mandatory for the given parameters after the power of the tag exceeds a threshold level. It has been concretely demonstrated by equations that phase shift modulation has the potential to increase speed. This potential can be implemented without changes from the EPC Class I Gen II rules and generally without changes in communication distance. Depending on the time at which the average peak power consumption on the tag occurs during communication, increasing the speed may require sacrificing some communication distance. Phase shift keying modulator varactor size reduction opportunity has been shown by equations to shrink die area. Depending on peak power consumption during communication, it can be exploited completely or partially.