Elektrik Elektronik Fakültesi

Bu topluluk için Kalıcı Uri

http://hdl.handle.net/11527/18000

Gözat

Yazar "Aksoy, Levent" ile Elektrik Elektronik Fakültesi'a göz atma
  • Öge
    Novel methods for efficient realization of logic functions using switching lattices
    (IEEE Transactions on Computers, 2019) Aksoy, Levent ; Altun, Mustafa ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communications Engineering
    Two-dimensional switching lattices including four-terminal switches are introduced as alternative structures to realize logic functions, aiming to outperform the designs consisting of one-dimensional two-terminal switches. Exact and approximate algorithms have been proposed for the problem of finding a switching lattice which implements a given logic function and has the minimum size,i.e., a minimum number of switches. In this article, we present an approximate algorithm, called JANUS, that explores the search space in a dichotomic search manner. It iteratively checks if the target function can be realized using a given lattice candidate, which is formalized as a satisfiability (SAT) problem. As the lattice size and the number of literals and products in the given target function increase, the size of a SAT problem grows dramatically, increasing the run-time of a SAT solver. To handle the instances that JANUS cannot cope with, we introduce a divide and conquer method called MEDEA. It partitions the target function into smaller sub-functions,finds the realizations of these sub-functions on switching lattices using JANUS, and explores alternative realizations of these sub-functions which may reduce the size of the final lattice. Moreover, we describe the realization of multiple functions in a single lattice. Experimental results show that JANUS can find better solutions than the existing approximate algorithms, even than the exact algorithm which cannot determine a minimum solution in a given time limit. On the other hand, MEDEA can find better solutions on relatively large size instances using a little computational effort when compared to the previously proposed algorithms. Moreover, on instances that the existing methods cannot handle, MEDEA can easily find a solution which is significantly better than the available solutions.
  • Öge
    Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
    (IEEE, 2019) Safaltin, Serzat ; Gencer, Oguz ; Morgul, M. Ceylan ; Aksoy, Levent ; Gurmen, Sebahattin ; Moritz, Csaba Andras ; Altun, Mustafa ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication Engineering ; Metallurgical and Materials Engineering ; Nanoscience and Nanoengineering
    Our European Union’s Horizon-2020 project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Within the project, we investigate different computing models based on either two-terminal switches, realized with field effect transistors, resistive and diode devices, or four-terminal switches. Although a four-terminal switch based model offers a significant area advantage, its realization at the technology level needs further justifications and raises a number of questions about its feasibility. In this study, we answer these questions. First, by using three dimensional technology computer-aided design (TCAD) simulations, we show that four-terminal switches can be directly implemented with the CMOS technology. For this purpose, we try different semiconductor gate materials in different formations of geometric shapes. Then, by fitting the TCAD simulation data to the standard CMOS current-voltage equations, we develop a Spice model of a four-terminal switch. Finally, we successfully perform Spice circuit simulations on four-terminal switches with different sizes. As a follow-up work within the project, we will proceed to the fabrication step.
  • Öge
    A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices
    (IEEE, 2019) Aksoy, Levent ; Altun, Mustafa ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication Engineering
    In recent years the realization of a logic function on two-dimensional arrays of four-terminal switches, called switching lattices, has attracted considerable interest. Exact and approximate methods have been proposed for the problem of synthesizing Boolean functions on switching lattices with minimum size, called lattice synthesis (LS) problem. However, the exact method can only handle relatively small instances and the approximate methods may find solutions that are far from the optimum. This paper introduces an approximate algorithm, called JANUS, that formalizes the problem of realizing a logic function on a given lattice, called lattice mapping (LM) problem, as a satisfiability problem and explores the search space of the LS problem in a dichotomic search manner, solving LM problems for possible lattice candidates. This paper also presents three methods to improve the initial upper bound and an efficient way to realize multiple logic functions on a single lattice. Experimental results show that JANUS can find solutions very close to the minimum in a reasonable time and obtain better results than the existing approximate methods. The solutions of JANUS can also be better than those of the exact method, which cannot be determined to be optimal due to the given time limit, where the maximum gain on the number of switches reaches up to 25%.