Ac-coupled supply modulator desıgn ın 130 nm PD-SOI technology

Abstract

High peak-to-average values (PAPR) of modern telecommunications standards tend to drop the efficiency of the power amplifiers. The drop in efficiency causes excessive power consumption, which leads to a shortened battery life for mobile systems. As a result, envelope-tracking supply modulator (ETSM) systems are developed to improve power amplifier efficiency by varying their supply voltage. There are different envelope-tracking supply modulator topologies in the literature that combine different amplifier structures with each other. The most popular topologies can be considered hybrid topologies, which take advantage of using two amplifiers in parallel with each other. This hybrid structure allows high-frequency components to be provided by the linear amplifier while low-frequency power is provided by a highly efficient switching amplifier. The linear amplifier is generally designed with a Class AB output driver, which increases the driving capability and reduces the power consumption of the linear amplifier. A buck converter is mostly used as a switching amplifier to generate DC current for the load. In the literature, a hysteretic control loop is commonly used to control the buck converter with the linear amplifier, and an additional dc-dc converter is added to control the supply voltage of the linear amplifier. To improve efficiency, AC-coupled hybrid topologies are introduced to lower the power consumption of the linear amplifiers. In this thesis, an AC-coupled hybrid ETSM is designed for 5G cellular vehicle-to-everything (C-V2X) systems that support up to 40 MHz of baseband bandwidth. The system consists of a proposed operational amplifier, a switching amplifier, a current-mode hysteretic buck converter to control the supply of the linear amplifier, a proposed zero-current detection (ZCD) current to detect the reverse current flowing through the inductor, and low-dropout regulators (LDO) for supplying the internal analog circuits. The ETSM is implemented in a 130 nm partially depleted (PD) silicon on insulator (SOI) process, and the die size is 3.051 mm2.