Design of a mixer first receiver front-end

Abstract

Modern wireless communication systems requires high performance transmitter and receivers. Evolving very large scale integration (VLSI) technologies makes compact and high speed chips possible. Multiple input multiple output (MIMO) systems or systems using beamforming use more than one transmitter and receiver or focusing the beam to the receiver. These communications systems require highly linear and low power receivers. In a conventional receiver architecture, signal chain starts with a low noise amplifier (LNA) to amplify small input amplitude with adding little amount of noise. After that a mixer is used for down converting the frequency to base band. Then this low frequency signal is amplified and filtered by a base band amplifier. Finally an analog to digital converter (ADC) is used to digitize the data and it is sent to digital processing blocks. In this thesis, a highly linear and low power receiver front-end is designed. Unlike the conventional receiver architectures, mixer first receivers are natural candidates for highly linear receivers because the architecture does not have an LNA as the first block in the chain. This makes the architecture popular for MIMO systems or systems using beamforming where the input power coming to the receiver is large and hence these systems require high linearity. Also, since large number of TX and RX are used in MIMO systems, reducing the power consumption of the chips became crucial. Removing LNA brings an advantage in terms of linearity but it has worse noise performance. This work is a part of TUBITAK 1001 project which aims to operate this receiver at cryogenic temperatures and compensate the noise performance of the mixer first receiver by decreasing the temperature. The architecture proposed in this thesis includes a 4-path filter consists of double balanced passive mixers followed by active feedback transimpedance amplifiers (TIA). An off chip balun is used to convert single ended input signal to differential. Input matching is realized by series resistors which is a method that enhances switch linearity. Also, 25% duty cycle square waves with 4 phases are generated on the chip for driving mixer's gate. Only local oscillator (LO) signal is supplied externally. TIA has 4bit control to arrange the gain of the amplifier and hence the receiver. Moreover, a feed forward automatic gain control loop is presented to control the gain of the receiver automatically. In this loop, a peak detector is senses the input signal and produce a DC voltage according to input amplitude. It is followed by an analog to digital converter (ADC) that directly digitizes this value. Finally, a gain mapping logic is presented to process this data and controls the transimpedance amplifier's gain. In this thesis, a high linearity and low power mixer first receiver front-end is designed. Rf input frequency is determined as 2- 3 GHz and base band frequency is 25 MHz. Quite high linearity results such as-2.15 dBm P1 dB value and 11 dBm IIP3 are obtained. Also, 4 bit gain control is possible using variable gain TIA. Maximum and minimum gain of the receiver is 24 dB and 5 dB respectively. Minimum noise figure along the band at maximum gain mode is 15.9 dB. Total static power dissipation including 4-path filter, LO generation and automatic gain control loop is 11.1 mW and 5.4 mW for maximum and minimum gain modes respectively. 1.2 V supply voltage and 65 nm bulk CMOS technology is used for this design. In this way, a high linearity and low power mixer first receiver front-end including an automatic gain control loop is designed.