High-level synthesis of a hardware accelerator for quaternion to Euler angles conversion

Abstract

This master's thesis aims to design and synthesize a hardware accelerator that can perform the transformation from quaternions to Euler angles. Quaternions are a four-component number system commonly used in 3D graphics, space flight control, robotics, and many other fields. They are used to define and calculate rotations in three-dimensional space and can be converted to Euler angles. Euler angles are used to define the orientation of objects in three-dimensional space and can be used to represent the orientation of aircraft. Controllers based on quaternions or Euler angles can be designed for aircraft control. While the use of quaternion representation is preferred due to potential singularity issues that may arise with the use of Euler angles, it is necessary to convert from quaternions to Euler angles when designing a controller that controls Euler angles. Therefore, a hardware accelerator that can perform the transformation from quaternions to Euler angles is needed. High-level synthesis (HLS) is a design methodology that allows designers to create digital hardware designs using high-level programming languages such as C, C++, or MATLAB, or graphical environments such as Simulink, instead of hardware description languages (HDL) like Verilog or VHDL (VHSIC Hardware Description Language). HLS tools can automatically generate the relevant HDL code and have the ability to perform optimizations such as resource sharing and timing to improve performance and reduce application costs, making it an effective method for hardware design. Prior to starting the design work, a literature review was conducted and the necessary resources were identified. The methods used in these resources were examined in detail. As a result of the examination, the advantages and disadvantages of the methods used were analyzed, and the methods to be used in the thesis work were decided. The design process started from the lowest level to achieve the goal of the thesis. In the thesis study, the design of the basic operators, addition, subtraction, multiplication, and division were taken as the starting point. These operations were implemented using single-precision floating-point arithmetic in the IEEE 754 standard. Later, blocks designed for the transformation of quaternions to Euler angles were added. These blocks include functions such as inverse tangent and sine and are necessary for the conversion from quaternions to Euler angles. During the design of the blocks containing inverse tangent and sine functions, the basic operators initially created were used. At every stage of the design, verification processes have been carried out to ensure the reliability of the created blocks. Standard blocks belonging to Simulink have been used as references for these verification processes. As a result of the design stages and the verifications conducted, a high-level synthesis of a hardware accelerator that can perform transformation from quaternions to Euler angles has been produced. This study consists of five sections that describe the stages of the thesis. The remaining part of the summary will cover the content of these sections. The first chapter presents a general introduction to the topic of the thesis. The need for the study conducted in the thesis and the methodology used have been expressed in a general manner. In the first chapter, a subsection has been created, and the aim of the thesis has been clearly stated. The second chapter discusses the methods used in the thesis. An introduction to high-level synthesis is presented, and its benefits on hardware design are discussed. A brief overview of field-programmable gate arrays and their structure is given. Then, floating-point arithmetic and the IEEE 754 standard used for floating-point representation are explained. Two different floating-point representations shaped by this standard, namely single-precision (32-bit) and double-precision (64-bit), are conveyed. The last part of the second chapter focuses on how quaternions express orientation and how to obtain the equations used for converting from quaternions to Euler angles. The third section encompasses the design process of the block that converts quaternions to Euler angles. Firstly, the designs of the basic operators are explained. Detailed information on the operation and flow diagram of the operator that performs addition and subtraction, one of the fundamental operators, is provided. Then, the operator that performs multiplication, which has a complex design, is explained. The method of multiplication is shown, and the design process is explained. Later in the section, algorithms that can be used for division are introduced, and the flowchart of the selected algorithm for the design is provided. In the penultimate part, the methods found in the literature for the implementation of inverse trigonometric functions are explained. In the same part, the stages of determining the methods to be used in the thesis and the error characterizations are presented in detail. In the last part, the accuracies of the designed blocks are compared with Simulink blocks. The fourth chapter covers the post-design processes. Firstly, the production process of the automatic hardware description language code and the settings used in this process are explained. Then, the results of the verification model created to test the accuracy of the generated code are compared. Finally, the results related to resource usage and performance are presented by performing the synthesis process. The results presented are not only for the block that converts quaternions to Euler angles, but also for every block created up to this stage. In the fifth and final section, the results obtained in the thesis study have been extensively evaluated. As a result of the evaluations, it has been observed that the standard block in Simulink which provides transformation from quaternion to Euler cannot currently be generated into hardware code and its not synthesizable. Therefore, it is important to be able to generate and synthesize the hardware code for this block that transforms from quaternion to Euler, which emerged as a result of the study. Possible future work in this area and directions in which the current study can be further developed have been expressed as a result of the evaluations.