Design of a highly efficient and linear driver power amplifier for 5G applications

Abstract

Wireless communication systems enable data transmission from one point to another through non-physical connections, primarily using radio frequency signals. Transmitters use power amplifiers to ensure the transmitted signal reaches the receiver with adequate strength. Power amplifiers are the components with the highest power consumption in a transmitter system, making their performance critical. Key performance parameters include linearity, gain, efficiency, output power, and bandwidth. Power amplifiers require sufficient input power for efficient operation, often necessitating a multi-stage configuration, with a driver stage followed by an output stage. Modern wireless systems like 5G employ complex modulation techniques involving amplitude and phase variations, resulting in signals with high PAPR ranging from 6 to 15 dB. Conventional PA designs are optimized for peak power efficiency, but efficiency decreases significantly at back-off levels due to high PAPR signals. Addressing this issue necessitates innovative techniques, often focused on the output stage. However, the entire system's efficiency is also influenced by the driver stage, which traditionally uses high-linearity designs with moderate efficiency. Enhancing driver stage efficiency while maintaining adequate linearity can improve overall system performance. This thesis proposes a novel approach to designing a highly efficient and linear driver power amplifier by operating in the nonlinear deep Class AB region. While traditional driver power amplifiers prioritize linearity, this design integrates supply modulation to optimize the drain bias voltage, improving back-off efficiency without significantly compromising linearity. The driver power amplifier was designed and simulated in Advanced Design System software, employing a CGH40006P GaN HEMT transistor on a RO4350B substrate. The PA operates at 3.5 GHz with a -2.85 V gate and 20 V drain bias, achieving deep Class AB operation. The design includes sub-circuit blocks for biasing and stability, optimized for linearity and efficiency. Load/source pull simulations determined the impedance for maximum power-added efficiency used in IMN and OMN. Simulations indicate that the driver power amplifier achieves a PAE of 63.36%, an output power of 35.4 dBm, and a small signal gain of 16.2 dB at 3.5 GHz. Moreover, the output phase change is only 16° up to the 3 dB compression point. For a modulated 5G NR signal with an 8.5 dB PAPR and 40 MHz bandwidth, the driver power amplifier delivers an ACPR of -31.62 dBc and an EVM of 5.3%. Supply modulation across 10–20 V improves back-off efficiency by approximately 15% and 20% at 12 dB and 9 dB back-off levels. These results demonstrate the feasibility of integrating nonlinear, high-efficiency driver power amplifiers into modern communication systems.