A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays
A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays
dc.contributor.author | Peker, Furkan | |
dc.contributor.author | Altun, Mustafa | |
dc.contributor.department | Elektronik ve Haberleşme Mühendisliği | tr_TR |
dc.contributor.department | Electronics and Communication Engineering | en_US |
dc.date.accessioned | 2019-05-22T13:12:00Z | |
dc.date.available | 2019-05-22T13:12:00Z | |
dc.date.issued | 2018 | |
dc.description.abstract | Nano-crossbar arrays are area and power efficient structures, generally realized with self-assembly based bottom-up fabrication methods as opposed to relatively costly traditional top-down lithography techniques. This advantage comes with a price: very high process variations. In this work, we focus on the worst-case delay optimization problem in the presence of high process variations. As a variation tolerant logic mapping scheme, a fast hill climbing algorithm is proposed; it offers similar or better delay improvements with much smaller runtimes compared to the methods in the literature. Our algorithm first performs a reducing operation for the crossbar motivated by the fact that the whole crossbar is not necessarily needed for the problem. This significantly decreases the computational load up to 72% percent for benchmark functions. Next, initial column mapping is applied. After the first two steps that can be considered as preparatory, the algorithm proceeds to the last step of hill climbing row search with column reordering where optimization for variation tolerance is performed. As an extension to this work, we directly apply our hill climbing algorithm on defective arrays to perform both defect and variation tolerance. Again, simulation results approve the speed of our algorithm, up to 600 times higher compared to the related algorithms in the literature without sacrificing defect and variation tolerance performance. | en_US |
dc.description.sponsorship | This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skodowska-Curie grant agreement No 691178. This work is supported by the TUBITAK-Career project #113E760 | en_US |
dc.identifier | Volume 4 | en_US |
dc.identifier | Issue 4 | en_US |
dc.identifier | Papers 522 - 532 | en_US |
dc.identifier.citation | F. Peker and M. Altun, "A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays," in IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 4, pp. 522-532, 1 Oct.-Dec. 2018. doi: 10.1109/TMSCS.2018.2829518 | en_US |
dc.identifier.issn | 2332-7766 | |
dc.identifier.uri | http://hdl.handle.net/11527/18009 | |
dc.identifier.uri | https://doi.org/10.1109/TMSCS.2018.2829518 | |
dc.language.iso | en | tr_TR |
dc.publisher | IEEE | en_US |
dc.relation | IEEE Transactions on Multi-Scale Computing Systems | en_US |
dc.relation.ispartofseries | Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer (NANOxCOMP) | en_US |
dc.source.uri | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8345304&isnumber=8630102 | |
dc.subject | Nano-crossbar Arrays | en_US |
dc.subject | Variation Tolerance | en_US |
dc.subject | Defect Tolerance | en_US |
dc.subject | Worst-case Delay Optimization | en_US |
dc.title | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays | en_US |
dc.type | Preprint | en_US |
dc.type | Article | en_US |
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