A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays
A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays
Tarih
2018
Yazarlar
Peker, Furkan
Altun, Mustafa
Süreli Yayın başlığı
Süreli Yayın ISSN
Cilt Başlığı
Yayınevi
IEEE
Özet
Nano-crossbar arrays are area and power efficient structures, generally realized with self-assembly based bottom-up
fabrication methods as opposed to relatively costly traditional top-down lithography techniques. This advantage comes with a price:
very high process variations. In this work, we focus on the worst-case delay optimization problem in the presence of high process
variations. As a variation tolerant logic mapping scheme, a fast hill climbing algorithm is proposed; it offers similar or better delay
improvements with much smaller runtimes compared to the methods in the literature. Our algorithm first performs a reducing operation
for the crossbar motivated by the fact that the whole crossbar is not necessarily needed for the problem. This significantly decreases
the computational load up to 72% percent for benchmark functions. Next, initial column mapping is applied. After the first two steps that
can be considered as preparatory, the algorithm proceeds to the last step of hill climbing row search with column reordering where
optimization for variation tolerance is performed. As an extension to this work, we directly apply our hill climbing algorithm on defective
arrays to perform both defect and variation tolerance. Again, simulation results approve the speed of our algorithm, up to 600 times
higher compared to the related algorithms in the literature without sacrificing defect and variation tolerance performance.
Açıklama
Anahtar kelimeler
Nano-crossbar Arrays,
Variation Tolerance,
Defect Tolerance,
Worst-case Delay Optimization
Alıntı
F. Peker and M. Altun, "A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays," in IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 4, pp. 522-532, 1 Oct.-Dec. 2018.
doi: 10.1109/TMSCS.2018.2829518