MRC ve akım taşıyıcı elemanları ile devre sentezi

Abstract

Bu tezde literatürde MOSFET-C filtre tasannu olarak bilinen aktif filtre sentezi öne sürülmektedir. Aktif filtre elemanı olacak positif akım taşıyıcı bloğu ve direnç olarak Czamul tarafından öne sürülen MRC ( MOS Resistive Circuit ) bloğu kullanılmaktadır. MRC elemanı esasında Tsividis tarafından öne sürülen yapının değiştirilmiş şeklidir. Tsividis'in öne sürdüğü yapı dengeli yapıdaki işlemsel kuvvetlendiriciler ile kullanılabilmekte ve tam olarak lineer değildi, sadece tüm çift terimli tranzistor nonlineerlikleri yok edebilmektedir. Czarnul, Tsividis' in yapısına çapraz bağlı iki MOS elemanı daha ekleyerek MRC yarışım oluşturmuştur. Böylece MRC bloğu fiziksel olarak aynı ve eş boyuttaki dört MOS tranzistordan oluşan giriş fark gerilimini çıkışta fark akımına dönüştüren, iki kontrol geriliminin farkıyla orantılı bir admitans elemanı oluşturan bir yeni yapı olarak ortaya çıkmış olmaktadır. MRC elemanının akım-gerilim bağıntısından ortaya çıkan sonuçlar aşağıdaki gibi özetlenebilir: 1) Mobilite kanal boyunca sabit varsayılmaktadır. 2)Direnç değeri eşik gerilimine ve gövde etkisi terimine bağlı değildir 3) Direnç sadece fark gerilimi ile ayarlanır ve dinamik aralık kontrol gerilimlerini aynı anda arttırarak arttırılabilir. 4) Direnç değeri taban gerilimine bağlı değildir. MRC elemanı dengeli modda olmak ararımda değildir, sadece akım çıkışındaki uç gerilimlerinin aym potansiyelde olması gerekmektedir. Bu elemanın AinamiV aralığı vb küçük işaret yüksek frekans davranışının elverişliliği bu tezde tercih edilmesinin temel nedenidir. Aktif eleman olarak seçilen positif akım taşıyıcı tanun bağıntısı gereğince MRC ile kullanılmaya uygun olduğu için seçilmektedir. Ayaca positif akün taşıyıcıların band genişliği birkaç MHz ' 1er civarında olması da önemli bir avantajdır. Bölüm 1 ' de aktif filtre tasarımının pasif filtre tasarımına karşı üstünlüğü açıklandıktan sonra alam taşıyıcı vb CMOS direnç gerçeklemeye yönelik literatürdeki çalışmalar verilmektedir. Bölüm 2 ' de alam taşıyıcının vb MRC elemanının matematiksel modellenmesi verilmektedir. işlemsel kuvvetlendirici temelli bir positif akım taşıyıcı bu bölümde verilip bu topolojinin dinamik aralığı teorik ve pratik olarak verilmektedir. Bölüm 3 ' te transfer fonksiyonu gerçeklerken kullanılabilecek temel yapı taşlan sunulmaktadır. Bölüm 4'te universal filtre gerçeklemeye yönelik işaret akış diyagramı temelli bir yöntem sunulmuş vb daha sonra basamaklı devre simülasyonu için bir yöntem üzerinde yoğunlaşılmaktadır. Bölüm 5'te ise simülasyon vb MOS sayısı minimize etme yöntemi sunulmaktadır.

MOSFET-C circuits started as a Columbia University/ Bell Laboratories invention in 1981. By the time Prof. Ismail started working in the above area in 1984, Tsividis and his group had published several papers on MOSFET-C circuits ( Fully integrated active RC or MOS active RC circuits). These publications elaborated the principles of MOSFET-C circuits, gave experimental results on a high-performance MOSFET-C filter chip,and presented the analysis and compensation of nonidealities in such circuits, including intrinsic parasitic effects. m April 1985, Prof. Czamul invented a linear transconductor consisting of four triode-operated MOSFETs in analog continous operation as opposed to being used as switches with two control voltages, named as four-MOSFET transconductor or MOS resistive circuit (MRC), and presented several possible applications. He showed that these four MOSFETs could advantageously replace Tsividis' two MOSFETs. Coniinous-time filters have recently received attention in the context of MOS VLSI technology. A main reason for this is that a number of drawbacks associated with switched-capacitor techniques are absent in continous-time operation. Since continous time filters do not employ sampling, as do switched-capacitor filters, high- frequency noise is not aliased into the baseband. The sampling process in switched- capacitor circuits also has the practical problems of clock feedthrough and switch charge injection, which are difficult to predict and eliminate, especially at high frequences; such problems are nonexistent in continous time filtering. At high frequencies, a switched - capacitor filter requires antialiasing and smoothing filters with sharp cutoff characteristics, due to low dock-frequency-to-baseband-frequency ratios, which makes necessary sophisticated continous-time filtering methods. Since such methods must be developed anyway, it is then natural to consider implementing the whole filtering function with continous-time techniques. One continous -time technique that has provided high linearity and high precision at voice-band frequencies is the MOSFET-C technique. Low-frequency MOSFET-C filters may be implemented with the basic integrator building block of Tsividis' balanced structure with two MOSFETs. These transistors operate in the non-saturation region and act as voltage-controlled resistors. By matching the transistors and using a balanced output op-amp, all even terms of the transistor nonlinearity cancel, provided that the inputs are also balanced. The odd terms of the transistor nonlinearity are not rejected, but they are much smaller in magnitude than the remaining linear term and can be neglected for most filter VI applications. For elimination of both even and odd nonlinearities, assuming a bias- independent mobility, Czamul ' s structure with additive MOSFETs is required. The MOS transistor is not a simple resistor as assumed, but rather can be modeled as a uniform RC transmission line for small-signal inputs. The distributed capacitance of the MOS transistor, due to the gate oxide and depletion layer capacitances, produces a phase lag at the output of the two-transistor integrator. The two-port admitance parameters for a uniform RC transmission line are given below : Rt.sinhvSr _ coshVSt -1 -1 coshVSx t = Rt-Ct (1) The filters operated at low frequencies relative to 1/t of the MOSFET ' s, so that the transmission line nature of the MOS transistor can be modeled with approximate admitance parameters. Expanding each of the hyperbolic functions in (1) in a series and retaining only the first two terms result in the following : £+1 yn=y22= - t - Rt. ST + 1 yi2=y2i -1 (2) Although the four-transistor integrator is superior to the two-transistor integrator in terms of quality factor, the four-transistor design has two disadvantages which must be considered. First, the thermal noise at the integrator output is higher in the four transistor case, assuming identical integrating capacitances, identical 0>o and negligible op-amp noise. Second, the sensitivity of co0 to transistor mismatches is worse in the four-transistor design. Both effects become more severe as the difference between control voltages decreases. To introduce the proposed MOS resistive circuit (MRC), we assume that the MOS transistors used have a long n-channel and operate in the nonsaturation region. Complete expressions describing the MOS transistor channel current ID in nonsaturation region are given as below : ID=F(VD,Va)-F(Vs,VG) vu with K^nC'nT, y=-±-(2qpA*a)> F(Vx,VQ) = 2K(Va-VB-VFB-B)* (3) The symbols have the following meaning : VD, Vs, V0, VB drain, source, gate and substrate potentials with respect to the ground L,W length and width of the channel Vfb flat-band voltage (Db approximate surface potentials in strong inversion for zero backgatebias ix carrier effective mobility in the channel, assumed independent of the terminal voltages NA substrate doping concentration Cm gate oxide capacitance per unit area e, silicon dielectric constant q electron charge MRC is shown in Fig.l and mathematical expression for input voltages and output currents is given below : I, - 12 - 2K(VGA - VoXV, - V2) (4) Figure 1 MOS transistors realization of MRC Vlll To ire»*»"» the versatility of the current conveyor, a second version in which no current flows in terminal Y, was introduced in 1968. The CCII is described by : (5) Thus, terminal Y exhibits an infinite input impedance. The voltage at X follows that applied to Y, thus X exhibits a zero input impedance. The current supplied to X is conveyed to the high impedance output terminal Z where it is supplied with either positive polarity as in CCII+ or negative polarity as in CCII-. In this thesis, the main objective is to design any kind of filter characteristics by using CCII+ and MRC blocks. Therefore, in Section I active and passive circuit synthesis methods are compared. After that, reference works of various authors are described in the subject of both current conveyor and CMOS based resistance implamftntflrirtfi In Section 2, ideal mathematical definition of current conveyor is given as in (5). For small signal frequency performance analysis, Wilson1 s model is proposed for certain input and output conditions so as not to cause clipping problem. Additionally, another 100% feedback applied opaerational amplifier based high performance model for current conveyor is also proposed, since a Sum CMOS process current conveyor topology suitable for this model is given in this section. This current conveyor topology proposed by Sedra and Roberts has been used within the whole thesis. Due to this, dynamic range and frequency behaviour of this topology have been analysed. For dynamic range 3 main steps are used : 1) Connecting a resistor at Z terminal and varying the resistor at termimal X, a DC voltage between - 5 V and +5 V is sweeped. 2) Grounding terminal Z and varying the resistor at terminal X, a DC voltage between -5V and +5V is sweeped. 3) Connecting a resistor at X terminal and varying the raostor at terminal Z, a DC voltage between -5 V and +5V is sweeped. PSPICE subcircuit model for this topology is also given and the practical results are taken with repect to this. After that it is searched for the dynamic region theoretically and analitical results have been obtained for this topology. At last MRC eleman is introduced giving its current voltage defining equation. As indicated above, MOS transistors are modelled as transmission lines for high frequency small signall opearation. In Section 3, voltage mode blocks such as multiplication block, addition block, lossless integrator block and derivative blocks are introduced. Secondly current mode structures such as current copier block, integrator block and derivative block are IX introduced using MRC and current conveyor block together. This structures can be used for signal flow graph based synthesis explained in Section 4. After that two port elements consisted of MRC and CCÜ are obtained with the elements of voltage type generalized impedance converter ( VGIC ) and current type generalized impedance converter. In Section 4, synthesis with signal flow graph is introduced both for voltage and current mode operation. This synthesis demonstrates that quality factor and operating frequency can be adjusted independently from each other for second order realization. After that we are concentrated on synthesis based on passive ladder structure simulation. The steps that should be taken for the execution of ladder circuit synthesis as passive circuit simulation have been given systematically. It can be shown that the synthesis has been reduced to passive grounded impedance simulation. Additionally current mode ladder structures are also be introduced within the thesis, but they are likely to the voltage mode structures. In Section 5, simulation of 3. order low pass filter has been executed by PSPICE. Then gyrator based second order band pass filter realization is given. For the reduction of number of MOSFETs a method is proposed as below : 1) Since the currents of two MOS transistors, connected to the same external terminals and applied same control voltages are equal, for such MOS transistors it can be shown that both of them can be erased if one terminal of these MOS is connected to the same potential and other is connected to the V and I terminal of an INIC. 2) If the two MOS transistors' drain and source terminals, applied same control voltages, are connected to the same terminals, one of them can be erased and its admitance are taken as double of its nominal value.