Kapasitif eşik lojiği temelli analog sayısal çevirici

Abstract

Analog-sayısal ve sayısal-analog çevirici devrelerinin önemi her geçen gün artmaktadır. Teknolojik ve bilimsel gelişmelerin sayısal sistemlerinin kullanımım yaygınlaştırması ve bir çok probleme sayısal çözümler bulunması, sayısal-analog ve analog-sayısal çevirici devrelerinin kullanımını ve bu devrelerin tasarımı konusunda yapılan çalışmaları arttırmıştır. Konu üzerinde yapılan çalışmalara katkıda bulunması amacıyla, "Kapasitif Eşik Lojiği" temelli bir "Analog-sayısal Çevirici" devresinin tasarımı bu tez çalışmasında sunulmuştur. "Kapasitif Eşik Lojiği" devre yapılan 90'k yılların başında geliştirilmiştir ve çalışma esasları 1960'k yıllarda ortaya çıkan "Eşik Lojiği"ne dayanır. Benzerlerine göre çok daha küçük silisyum alanlarında lojflc devrelerin gerçeklenmesine imkan veren bu yapıların sağladığı faydalar, analog-sayısal çevirici devresi tasarımında da kullanılmıştır. Kapasitif eşik lojiği kapılarıyla analog giriş işareti belirli referans gerilimleriyle karşılaştırılır ve bu işlem devre yapısıyla belirlenen bir akış içinde hiç bir kontrol işaretine gerek duyulmaksızın yapılır. Tasarlanan analog-sayısal çevirici devresi benzerlerine, silisyum üzerinde gerçekleme alam bakımından üstünlük sağlamaktadır. Kapasitif eşik lojiği kapılarının gerçeklenmesinde, istenilmeyen ikincil etkilerin azaltılması için yeni devre yapılan önerilmiştir. Bu sayede analog-sayısal çevirici devresinin performansı da arttırılmıştır. Yük enjeksiyonu, besleme gerilimini bastırma oram ve devrelerin hızı konusunda iyileştirici çalışmalar yapılmıştır. Geliştirilen yapıların çalışması benzetim sonuçlan verilerek desteklenmiştir. Tasarım ortamının sunduğu imkanlarla, tasarlanan kapasitif temelli analog-sayısal çevirici devrenin serim öncesi ve serim sonrası benzetimleri yapılmış ve benzetim sonuçlan değerlendirilerek, yapılan çalışma bezerleri ile karşılaştırılmış, devrenin kullanım alanlan belirlenmiştir.

Analog-to-digital and digital-to-analog converters are widely used in today's electronic sytems. Growing demand for digital circuit based solutions and digital system designs in many branches of the electronic industry, make these converter circuits more essential. Recent advances in signal processing and silicon fabrication, make digital systems to become more extensively used in many applications, though interface to the analog world can only be done via analog-to-digital and digital-to- analog converters. Not only for electronic equipment manufacturers but also for circuit design and research groups, the converter circuits are becoming more attractive as development and research project, simply because of that, the projections made for the next few years are pointing the demand for converter circuits with higher resolution and higher conversion rates. A converter circuit which is a key stone in mixed-mode system design and must satisfy the needs of the system, in means of resolution, speed and cost. Considering these requirement as design criteria and planning to support the related research study done on the subject, a "Capacitive Threshold Logic Based Analog-to-Digital Converter" circuit is introduced in this thesis. "Threshold Logic" which was introduced in the early 60's, perform not only and/or primitives but any linearly separable Boolean functions using a single gate. This advantage of realizing Boolean functions in a shorter logic depth didn't find many application areas most probably due to the limited success achieved in developing a suitable threshold logic gate on silicon. In the early 90's "Capacitive Threshold Logic Gate" which is a capacitive and charge based implementation of a threshold logic gate, is introduced. Its satisfactory performance for many applications and smaller implementation area than its counterparts, make the gate more advantageous for VLSI designs. A capacitive threshold gate schematic is shown in Figure 1. The operation of the capacitive threshold logic gate is controlled by the clock signals <|>r and §E which are active in the "Reset" and "Eval" phases respectively. In the "Reset" phase the clock signal <|>r is logic- 1 and all of the inputs are connected to the reference voltage Vref. Meanwhile output of the first inverter is connected to its input and the voltage of the input node is forced to the inverter threshold. At the "Eval" phase, clock signal e is activated and all input signals are applied to the gate inputs and this cause the input node voltage of the first inverter to change. This voltage change is amplified by the XI cascade connected inverters and the outputs will take their logic values. Change in the input node voltage of the first inverter is given in expression (1). V2 Vn Figure 1 A capacitive threshold logic gate. ±Cj-(Vj-Vref) AV = M (1) 7=1 The main operation principle of the capacitive threshold logic based analog-to- digital converter circuit is that, analog input signal which is first sampled in the "Reset" phase is then compared with the appropriate reference voltages in the "Eval" duration and digital outputs are produced by the capacitive threshold logic gates. The comparison begins with the most significant bit and according to the result of the previous bit the rest of the gates adjust their reference voltages via control switches controlled bye the previous bits. Although the conversion is done according to a similar algorithm of the "Successive Approximation Analog-to- Digital Converters", no control signals, different than the "Reset" and "Eval" phase clocks, are used for the control of the conversion operation, and the outputs mount after successive ripplings in a single clock phase. Capacitive threshold logic based analog to digital converter is designed to have 8- bks output. This is equivalent to 20mV input resolution for the least significant bit, under 5 V supply operation. The trade-off between the unit capacitor value and the area of a threshold logic gate makes the conventional capacitive threshold logic gates impossible to be used in this design. In order to suppress the second order effects for needed accuracy of operation, unit capacitor have to be chosen a few hundreds of the minimum capacitor size allowed by today's typical CMOS processes. Novel sub-blocks' circuitry for capacitive threshold gate architecture is introduced. The second order effects for a capacitive threshold logic gate which are mainly charge-injection effects, low power supply rejection ratio and speed are tried to be..managed with the hardware used, while keeping the design complexity alike. Capacitive threshold logic gates include high gain comparators. In the conventional Xll gate architecture, three cascade connected identical inverters are used for this purpose. The input of the first inverted is adjusted to its threshold voltage in the "Reset" phase by a MOS transistor shortening inverter's input and the output. During the "Eval" phase the voltage of input node, which is floating, of the inverter chain, is changed by capackively coupled input signals and the output takes its continuos value after the delay of the chain. Selecting small value capacitors for capacitive coupling, increase the effect of charge injected by the switch MOS transistor in the first inverter stage. The charge injection cause the floating input node voltage to decrease and suppress the voltage perturbation of the input signals. In order to avoid charge injection effect a differential comparator is designed. The amount of charge injected on one side is also injected on the other differential input and the difference between two inputs are allowed to be changed with the input voltage differences practically. Using a negative feedback, biasing of the comparator is stabilized and the power supply rejection is increased. This makes the capacitive threshold logic gate more suitable for mixed mode integrated circuit implementations. Comparator circuit schematic is shown in Figure 2. It has mainly three cascade stages. The first one is a self biased differential amplifier. Both of its inputs can be short circuited to its outputs via MOS tranzistors in order to bias the comparator inputs at the "Reset" phase. The second stage is a well known symetrical operational transconductance amplifier. This stage enables an high differential voltage gain and amplifies the output of the first stage nearly to the supply voltage rails. The last stage is the output stage whics is build up with two inverters. Output stage guarantees the apropriate logic levels to be seen at the outputs. Stability and metastability which are two important issues especially at flash analog-to-digital converter design, are prevented by the suitable output stage design of the comparator blocks also. The gain of three stages are given in expressions from (2) to (4). In the expresions "gm" is the transconductance of the related gain tranzistor, "r0" is the output resistance of the tranzistor connected to the output node and "B" is the tranzistor transconductance ration of the current mirrors used in second stage. X Ih Ü R^î RR Vtn_i p-i - ^ t T ]H "1 r Tt J İ1 > Hn H i - DvouLi|P Figure 2 Comparator circuit schematic. Xlll Kvd = gm. To (2) To Kvd = B-gm- - 2 (3) Kv = gm. Vo (4) In order to determine the effects of process parameters' changes, on the operation of the comparator circuit, "Monte Carlo" simulations are made. Equivalent input refered offset, which is called also as "Random Offset" is found to be 1.28mV and 0.57 lmV, for %5 percent and 0.1 um change in the tranzistor channel dimensions, respectively. On the other hand, systematic offset of the comparator is practically zero as a result of its symetrical architecture. The converter circuit is porposed to be implemented with 0.8um AMS CMOS technology. Design is carried out using CADENCE Design Framework-II analog design tools. The top-level schematic of the circuit is shown in Figure 3. All the capacitors used are equal and 360fF. Reference voltages are produced by a R-2R resistor circuit whic is also shown in the figure. Figure 3 Analog-to-digital converter circuit top-level schematic. XIV Post-layout simulations yields 300KS/s throughput for 8-Bit operation. The active silicon area of the capacitive based analog-to-digital converter is only 0.08um2. Another remarkable property of the capacitive threshold logic based analog-to- digital converter is its low power consumption. The power consumption of the circuit is nearly 15mW. Its small area and low-power consumption makes the converter suitable for embedding into standard cell based integrated circuit designs with a low silicon cost. All the signal interface at the control input and at the converter output is CMOS compatible. A post-layout simulation result is shown in Figure 4 corresponding to the input voltage of "VDD x[0.1010 1010 \\" volts. -e e- 0.0 r x100 6.0, x100 6.0, -1.0IQ X100 6.0 Transient Response : /Vd1 g : /Vd2 : /Vd3 -1 <7lN,U_J,,, x10^ 6.0 » : ^dA ' ' ' '° i i i i i i t- X100 6.0 ¦ : ^d5 -1 KH,Ui il », i J x100 6.0 ¦ ; ^dS __ -1 (TiPirU,L»_ _1 I I ' '*¦ X100 6.0 ' : ^d7 - 1 ClR lUJ il c i) I I I I tl I I I, I, ID A, I I I x100 g 0 o : A/d8 -1.0IQJI* I I I tli i, i - i- 'i I | I | | | | i ' i i. i i i - X10 0. 1. 2. 3. time -6 Figure 4 A post-layout simulation result. The capacitive threshold logic based analog-to-digital converter meet the performance requirements for being used in audio systems, some signal processing applications and industrial automation circuitry. The converter is ready for fabrication and prototyping. Then, detailed test measurements have to be made on the prototypes and test result have to be checked to verify the design. Measurements related to the errors which are devised for the analog-to-digital converter circuits have to be checked. Oflset error, differential and integral non- linearity errors are the three basic errors meet at the analog-to-digiatl converter design. XV