A novel current reuse low noise amplifier design operating in 10-18 ghz

Abstract

Low-noise amplifiers (LNAs) are essential components extensively utilized in commercial and military applications, including communication, radar, and remote sensing systems. Although their fundamental purpose is signal amplification, the defining characteristic of these structures is the specialized design of the input impedance matching, which prioritizes achieving the minimum noise figure (NF) over maximizing power transfer or minimizing input reflection. While NF remains the primary critical factor in LNA design, the increasing complexity of communication systems, the widespread use of modulated signals, and advancements in radar technology have heightened the demand for front-end designs with high dynamic range, making the linearity parameter equally significant. Furthermore, as satellite technologies advance, constraints on battery life and space-based energy generation necessitate wideband, low-power receiver architectures, thereby imposing significant pressure on the power consumption of LNAs. To meet these evolving demands while maintaining a low noise figure, the current-reuse LNA topology has emerged as a relatively new approach, with ongoing research across GaAs, CMOS, and GaN processes. The current-reuse topology is based on redirecting the DC current used in the output stage to supply the input stage. In this configuration, the sources of the output-stage devices are connected to the ground via DC-blocking capacitors, while the drains of the input-stage transistors are connected to the sources of the output-stage transistors through RF-choke inductors. This situation allows for significant savings in external DC power consumption—typically consumed by blocks where small-signal gain and NF are critical but high linearity is not—without degrading the noise figure. Despite its low power consumption and optimized NF, the current-reuse topology often suffers from linearity issues due to the loss of output-stage voltage headroom. Increasing the current to improve linearity typically causes a deviation from the optimal VGS required for NFmin; thus, the linearity of the structure remains limited by the dimensions and current levels that allow for the minimum noise figure. In the design methodology developed in this thesis, this problem is addressed by implementing a distributed amplifier (DA) structure in the input stage. By adjusting the number of sections in the distributed amplifier, each transistor can be biased at the specific VGS that yields the NFmin value, regardless of the output-stage current for linearity. Consequently, the mandatory trade-off between linearity and noise figure can be adjusted flexibly to meet the design requirements. A methodical approach is also proposed for implementing the developed topology. In this context, the design and layout were performed using a commercial GaAs 150 nm process. The final circuit, including parasitic effects obtained from EM simulations, was analyzed using the Small-Signal and Large-Signal (Harmonic Balance) methods in Advanced Design System (ADS). Post-design results demonstrate a 25 dB gain across the 10-18 GHz band, with a P1dB of 17 dBm and an OIP3 of 29 dBm. While consuming approximately 250 mW (51.8 mA at a 5 V supply), the noise figure remained below 2 dB at the worst-case point. Considering future fabrication and testing phases, the design was finalized with dimensions of 1500 μm × 2300 μm, suitable for production and packaging.