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dc.contributor.authorTunali, Onur
dc.contributor.authorMorgül, M. Ceylan
dc.contributor.authorAltun, Mustafa
dc.identifierVolume 38en_US
dc.identifierIssue 5en_US
dc.identifierPapers 22–31en_US
dc.identifier.citationO. Tunali, M. C. Morgul and M. Altun, "Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation," in IEEE Micro, vol. 38, no. 5, pp. 22-31, Sep./Oct. 2018. doi: 10.1109/MM.2018.053631138tr_TR
dc.description.abstractIn this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs.tr_TR
dc.description.sponsorshipThis work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178, and supported by the TUBITAK-Career project #113E760tr_TR
dc.relationIEEE Microen_US
dc.relation.ispartofseriesSynthesis and Performance Optimization of a Switching Nano-Crossbar Computer (NANOxCOMP)en_US
dc.subjectLogic functionsen_US
dc.subjectLogic designen_US
dc.subjectHeuristic algorithmsen_US
dc.subjectLogic arraysen_US
dc.subjectLogic gatesen_US
dc.titleDefect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluationen_US
dc.contributor.departmentElektronik ve Haberleşme Mühendisliğitr_TR
dc.contributor.departmentElectronics and Communication Engineeringen_US
Appears in Collections:Elektronik ve Haberleşme Mühendisliği

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