Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

Basit Görünüm
dc.contributor.authorTunali, Onur
dc.contributor.authorMorgül, M. Ceylan
dc.contributor.authorAltun, Mustafa
dc.contributor.departmentElektronik ve Haberleşme Mühendisliği
dc.contributor.departmentElectronics and Communication Engineering
dc.date.accessioned2019-05-22T10:53:38Z
dc.date.available2019-05-22T10:53:38Z
dc.date.issued2018
dc.description.abstractIn this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs.
dc.description.sponsorshipThis work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178, and supported by the TUBITAK-Career project #113E760
dc.identifierVolume 38
dc.identifierIssue 5
dc.identifierPapers 22–31
dc.identifier.citationO. Tunali, M. C. Morgul and M. Altun, "Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation," in IEEE Micro, vol. 38, no. 5, pp. 22-31, Sep./Oct. 2018. doi: 10.1109/MM.2018.053631138
dc.identifier.issn1937-4143
dc.identifier.urihttp://hdl.handle.net/11527/18008
dc.identifier.urihttps://doi.org/10.1109/MM.2018.053631138
dc.language.isoen
dc.publisherIEEE
dc.relationIEEE Micro
dc.relation.ispartofseriesSynthesis and Performance Optimization of a Switching Nano-Crossbar Computer (NANOxCOMP)
dc.source.urihttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8474945&isnumber=8474938
dc.subjectMemristors
dc.subjectLogic functions
dc.subjectDelays
dc.subjectLogic design
dc.subjectHeuristic algorithms
dc.subjectLogic arrays
dc.subjectLogic gates
dc.titleDefect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
dc.typePreprint
dc.typeArticle

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