Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

dc.contributor.author Tunali, Onur
dc.contributor.author Morgül, M. Ceylan
dc.contributor.author Altun, Mustafa
dc.contributor.department Elektronik ve Haberleşme Mühendisliği tr_TR
dc.contributor.department Electronics and Communication Engineering en_US
dc.date.accessioned 2019-05-22T10:53:38Z
dc.date.available 2019-05-22T10:53:38Z
dc.date.issued 2018
dc.description.abstract In this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs. tr_TR
dc.description.sponsorship This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178, and supported by the TUBITAK-Career project #113E760 tr_TR
dc.identifier Volume 38 en_US
dc.identifier Issue 5 en_US
dc.identifier Papers 22–31 en_US
dc.identifier.citation O. Tunali, M. C. Morgul and M. Altun, "Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation," in IEEE Micro, vol. 38, no. 5, pp. 22-31, Sep./Oct. 2018. doi: 10.1109/MM.2018.053631138 tr_TR
dc.identifier.issn 1937-4143
dc.identifier.uri http://hdl.handle.net/11527/18008
dc.identifier.uri https://doi.org/10.1109/MM.2018.053631138
dc.language.iso en tr_TR
dc.publisher IEEE tr_TR
dc.relation IEEE Micro en_US
dc.relation.ispartofseries Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer (NANOxCOMP) en_US
dc.source.uri http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8474945&isnumber=8474938
dc.subject Memristors en_US
dc.subject Logic functions en_US
dc.subject Delays en_US
dc.subject Logic design en_US
dc.subject Heuristic algorithms en_US
dc.subject Logic arrays en_US
dc.subject Logic gates en_US
dc.title Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation en_US
dc.type Preprint en_US
dc.type Article en_US
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