Model-based design and implementation of schedulers in ARINC-664 end system as a system on chip

Abstract

Ethernet-based deterministic network protocol that provides bounded delay and jitter using redundant communication among the avionics applications. Achieving the end-to-end bounded delay objectives requires that incoming Ethernet frames must be regulated according to the ARINC-664 standard. In ARINC-664, each rate-constrained flow, i.e., Virtual Link (VL), is regulated by using End Systems (ESs) and Bandwidth Allocation Gap (BAG). Each regulated VL must be served at a time, so a scheduling mechanism must be used when more than one queue is ready to be served. ARINC-664 standard does not specify the details of the scheduling algorithm. However, some algorithms are proposed in the literature for ARINC-664 scheduling. Field Programmable Gate Array (FPGA) is one of the most preferred implementation choices for ARINC-664 due to its low power consumption, low latency data transfer, and security advantages. Traditional FPGA development requires building design and verification with Hardware Description Languages (HDLs). Instead of this time-consuming FPGA development, using a model-based hardware design enables faster prototyping and testing environment. In this thesis, first, a Single Queue model is designed and developed in Simulink to provide a basic queueing infrastructure for ARINC-664 ES. Then, the ARINC-664 ES model is developed on top of the Single Queue model. The scheduling algorithms in ARINC-664 ES are designed and developed using HDL convertible components. The Smallest BAG (SB), the Smallest Size (SS), the Longest Queue (LQ), and the First-In-First-Out (FIFO) ARINC-664 ES scheduling algorithms are implemented. This implementation allows collecting the mean, standard deviation, and maximum of jitter performances of the scheduling algorithms. In addition, an ARINC-664 ES Dynamic Scheduler model whose components can be converted to HDLs and C/C++ is built. This model contains all the scheduling algorithms, and the user can switch among the scheduling algorithms while the model is operating.