A 65 nm CMOS low-power phase-locked loop design for 5g nr78 mobile applications

Abstract

The increasing demand for high-speed, low-latency communication in modern mobile systems necessitates the development of energy-efficient and high-performance frequency synthesizers. This thesis focuses on the design and analysis of a low-power phase-locked loop (PLL) architecture optimized for fifth-generation (5G) new radio (NR) n78 frequency band applications. The design is implemented using the Taiwan semiconductor manufacturing company (TSMC) 65nm complementary metal-oxide-semiconductor (CMOS) process and simulated via the Cadence Virtuoso. The study begins with an overview of the fundamental importance of PLLs within radio frequency (RF) transceiver systems. Subsequently, the necessary background information regarding the targeted 5G NR n78 band standards for the design is provided. A theoretical background is also developed to establish a solid understanding of PLL operation, including loop dynamics and stability criteria. In the sequel, mathematical noise modeling and time- and frequency-domain analysis are used to study system behavior. Additionally, several other analysis are discussed to observe and enhance the performance of the loop. The design methodology involves constructing individual PLL building blocks, including the phase-frequency detector, charge pump, loop filter, voltage-controlled oscillator and frequency divider. Individual block analyses are discussed to improve overall system performance, with a particular focus on reducing the phase noise of the loop. Trade-offs among power consumption, phase noise, and supply sensitivity are also examined. Following the successful design and simulation of each block, the components are integrated into a complete PLL loop. System-level simulations are conducted to verify functionality and evaluate performance against typical 5G standards. The design demonstrates effective trade-offs between power efficiency and noise performance. The implemented CMOS PLL effectively covers the n78 band with a 500 MHz tuning range and meets all the standard's requirements. This work is motivated by the lack of existing studies on CMOS-based PLLs explicitly designed for the n78 band in 5G NR systems according to literature review. The outcomes of the design architecture confirms the suitability for 5G n78 band applications. The final design achieves a phase noise of -116.8 dBc/Hz at 1 MHz offset and the total power consumption of 6.7968 mW.