LEE- Elektronik Mühendisliği Lisansüstü Programı

Bu topluluk için Kalıcı Uri

http://hdl.handle.net/11527/19263

Gözat

Konu "Analog tasarım" ile LEE- Elektronik Mühendisliği Lisansüstü Programı'a göz atma
  • Öge
    8 Gbps LVDS transmitter design in 22 nm FD-SOI for high speed chip-to-chip communication interfaces
    (Graduate School, 2024-06-04) Kurt, Alper ; Tekin, Ahmet ; 504211235 ; Electronics Engineering
    In recent years, tremendous advancements in the processing speed of microprocessors, motherboards, optical transmission links, and routers have expanded the off-chip data rates. The increasing demand for data bandwidth across electronic systems has led to significant innovations in wireline input/output (I/O) drivers. Various standards have been created by many institutions to manage the difficulties of high-speed wireline data transmission. The aggressive technology scaling not only increased the interest in I/O speed but also it additionally contributed noticeably to the enhancement in data rate and power efficiency of the wireline links. Even though the I/O data rates and data processing power have been improved by the technology scaling, the bandwidth of the copper links has not been scaled in the same manner. Therefore, the requirement for advanced equalization techniques has emerged in recent years to eliminate the corrosive effect of the channel such as inter-symbol interference (ISI) emerging at high frequencies. LVDS standard have been very popular among other communication standards due to its low power consumption, high noise immunity, high speed point-to-point data transmission, and good electromagnetic interference performance. LVDS is configured as a switched-polarity current generator. Optimum line impedance matching is achieved due to differential termination resistor at the receiver end of the system. Since LVDS transmits differential data, crosstalk and robustness of the link to common mode noise is extremely enhanced. The received digital data is represented with analog voltage swing at the output of the LVDS, which improves the data rate and also reduces power consumption. The channel is the physical medium that signal passes through from transmitter side to receiver side. Transmitted signal travels through various traces before reaching its destination. With the increase in frequency, line attenuation of this channel increases due to dielectric loss and skin effect. The channel behaves like a low pass filter which deteriorates the signal quality. first pre-cursor and post-cursor samples become very large due to Pulse dispersion from low-pass filtering, which makes detecting the bits that are transmitted in a sequence. This effects also generates intersymbol interference (ISI), which is interference of the transmitted symbol with the subsequent symbol due to distortion at high data rate. As a result, to overcome the corrosive effects of the channel equalization is needed. In general, pre-emphasis technique is used in transmitter side for channel equalization. In this thesis, 8 Gbps Low-Voltage Differential Signaling (LVDS) transmitter having controllable pre-emphasis and inductive peaking is designed for high speed chip-to-chip communication links. The transmitter system contains of pre-driver, core LVDS driver with Common Mode Feedback (CMFB) Amplifier, delay lines, auxiliary pre-driver and Pre-emphasis blocks. It has 1.225 V output common mode voltage which is adjustable between 0.98 V and 1.330. The output swing amplitude is between 230 mV and 350 mV. It consumes 20.248 mW power at 8 Gbps data rate which yields 2.531 pJ/bit energy efficiency. LVDS transmitter is implemented in 22 nm Fully Depleted Silicon on Insulator (FD-SOI) technology and the layout occupies 0.036 mm2 area including layout.