LEE- Elektronik Mühendisliği Lisansüstü Programı

Bu topluluk için Kalıcı Uri

http://hdl.handle.net/11527/19263

Gözat

Konu "ADC Fundamentals" ile LEE- Elektronik Mühendisliği Lisansüstü Programı'a göz atma
  • Öge
    Design and implementation of an 11-bit 50 ms/s flash-assisted successive approximation register ADC
    (Graduate School, 2023) Maden, Fatih ; Karalar, Tufan Coşkun ; 783612 ; Electronics Engineering Programme
    Modern electronic systems transmit, store, and process data. Pure analog solutions are no longer practical due to the increasing complexity of electronic systems. Thanks to advances in digital signal processing (DSP), signal processing and storage have moved from analog to digital domains. However, first of all, analog signals should be converted to digital signal in order to take advantages of DSP. Therefore, DSP systems are needed ADC. There are different ADC topologies in the literature because each system has different performance requirement. The most popular ADC architectures are flash, pipeline, SAR, delta-sigma and time-interleaved ADCs. Each of these architecture has own advantages and disadvantages in terms of resolution, sample rate etc. SAR ADC has been one of the most widely used ADC architectures over the past decade. Due to its largely digital structure, SAR ADC take advantage from CMOS technology scaling. SAR ADCs are generally preferred for medium accuracy, medium speed, and low power applications like biosensors, image sensors, and wearable devices because they have the highest energy efficiency of all moderate bandwidth, moderate resolution converters. However, resolution and speed of the SAR ADC is restricted by comparator offset and mismatch in the DAC. Therefore, many calibration and redundancy techniques have been proposed to improve SAR ADC resolution, but they increase design complexity and don't solve bandwidth issues. In this work a new method proposed in order to increase resolution of the SAR ADC without speed degradation. 11-bit flash assisted SAR ADC with a 50 Msps date rate designed and simulated in TSMC 65nm technology node. The working principle of the our design is similar to pipeline ADC. Conversion is completed in two cycles . In the first cycle SAR ADC sample the input signal and generate the most significant eight bit. In the second cycle, the residue voltage produced by the SAR ADC is amplified through the switch capacitor circuit and converted into three bits with the help of the flash ADC. Then output of the SAR ADC and flash ADC is aligned and 11-bit resolution is obtained. The thesis consists of five chapters, with the first chapter introducing the work and objectives. In the second chapter, background information about ADC design and commonly used ADC architectures are reviewed. In the third chapter, the architecture of the designed flash-assisted SAR ADC is explained. In chapter four, simulation results for the designed blocks are presented and interpreted. The thesis is concluded and compared with similar work in the fifth chapter.