Logic synthesis and defect tolerance for memristive crossbar arrays
Logic synthesis and defect tolerance for memristive crossbar arrays
dc.contributor.advisor | ||
dc.contributor.author | Tunali, Onur | |
dc.contributor.author | Altun, Mustafa | |
dc.contributor.authorID | https://orcid.org/0000-0002-3103-1809 | tr_TR |
dc.contributor.department | Electronics and Communication Engineering | en_US |
dc.date.accessioned | 2019-05-23T06:39:44Z | |
dc.date.available | 2019-05-23T06:39:44Z | |
dc.date.issued | 2018-04-23 | |
dc.description | This is a conference paper. | en_US |
dc.description.abstract | Contrary to abundant memory related studies of memristive crossbar structures, logic oriented applications are only gaining popularity in recent years. In this paper, we study logic synthesis, regarding both two-level and multi level designs, and defect aspects of memristor based crossbar architectures. First, we introduce our two-level and multi-level logic synthesis techniques. We elaborate on advantages and disadvantages of both approaches with experimental results regarding area cost. After that, we devise a defect model in alignment with the conventional stuck-at open and closed paradigm. In addition, we determine the effects of defects to the operational capacity of the crossbar. Furthermore, we propose a preliminary defect tolerant Boolean logic mapping approach. In order to evaluate our approach, we conduct extensive Monte Carlo simulations with industrial benchmarks. Finally, we discuss future directions concerning both existing two-level and prospective multi-level logic designs as well as defect tolerance with area redundancy. | en_US |
dc.description.sponsorship | This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skodowska-Curie grant agreement No 691178. This work is supported by the TUBITAK-Career project #113E760. | en_US |
dc.description.version | Published | |
dc.format.extent | 1-6 (6) | |
dc.identifier | 10.23919/DATE.2018.8342047 | |
dc.identifier.citation | O. Tunali and M. Altun, "Logic synthesis and defect tolerance for memristive crossbar arrays," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 425-430. doi: 10.23919/DATE.2018.8342047 , URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8342047&isnumber=8341968 | en_US |
dc.identifier.issn | 1558-1101 | |
dc.identifier.uri | http://hdl.handle.net/11527/18011 | |
dc.identifier.uri | ||
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.publisher | Istanbul Technical University | en_US |
dc.source | 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) | en_US |
dc.subject | Memristors | en_US |
dc.subject | Switches | en_US |
dc.subject | Logic functions | en_US |
dc.subject | Logic arrays | en_US |
dc.subject | Logic design | en_US |
dc.subject | logic circuits | en_US |
dc.title | Logic synthesis and defect tolerance for memristive crossbar arrays | en_US |
dc.type | Conference Paper |
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