Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
dc.contributor.author | Morgul, Muhammed Ceylan | |
dc.contributor.author | Peker, Furkan | |
dc.contributor.author | Altun, Mustafa | |
dc.contributor.department | Electronics and Communication Engineering | tr_TR |
dc.contributor.department | Elektronik ve Haberleşme Mühendisliği | tr_TR |
dc.date.accessioned | 2019-05-23T08:15:22Z | |
dc.date.available | 2019-05-23T08:15:22Z | |
dc.date.issued | 2016 | |
dc.description.abstract | In this study, we introduce an accurate capacitorresistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies. | tr_TR |
dc.description.sponsorship | This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178, and supported by the TUBITAK-Career project #113E760 | tr_TR |
dc.identifier | Pages 437-442 | en_US |
dc.identifier.citation | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays. (2016). 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium On, 437. https://doi.org/10.1109/ISVLSI.2016.100 | tr_TR |
dc.identifier.isbn | 978-1-4673-9039-2 | |
dc.identifier.issn | 2159-3477 | |
dc.identifier.uri | http://hdl.handle.net/11527/18017 | |
dc.identifier.uri | https://doi.org/10.1109/ISVLSI.2016.100 | |
dc.language.iso | en | tr_TR |
dc.publisher | IEEE | tr_TR |
dc.relation | IEEE Computer Society Annual Symposium on VLSI (ISVLSI) | en_US |
dc.relation | Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer(NANOxCOMP) | en_US |
dc.subject | Nano-crossbar array | tr_TR |
dc.subject | Circuit modeling | tr_TR |
dc.subject | Performance analysis | tr_TR |
dc.subject | Emerging technologies | tr_TR |
dc.subject | Post-CMOS | tr_TR |
dc.title | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays | tr_TR |
dc.type | Conference Paper | tr_TR |
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