High speed data acquisition techniques for pipelined analog to digital converters in IHP SiGe BiCMOS 0.13 µm

Abstract

The resolution of the analog-to-digital converter market may be categorized into 8-b, 10-b, 12-b, 14-b, 16-b, and other options. The incorporation of several resolutions arises from the demands of different applications. In 2018, the 12-b resolution lead the market for analog-to-digital converters. The 16-b type is expected to overtake and become the dominant force in the future. The use of 12-b for 5G connectivity presents a favorable opportunity for market expansion. Texas Instruments unveiled a groundbreaking ADC in May 2019, boasting the industry's largest bandwidth, lowest power consumption, and fastest sampling rate. This converter is anticipated to assist engineers in attaining optimal measurement precision for 5G testing, oscilloscopes, and direct X-band sampling in radar applications. In this work, a one way 11-b pipeline ADC, designed in a SiGe BiCMOS 0.13 μm, is presented. It has sampling frequencies up to 1.6 GS/s and can provide above 8-b ENOB for the low input signal frequency and 6.4-b ENOB for the highest input frequency of 799 MHz according to the simulation results obtained without calibration. For our ADC, sample-and-hold amplifier-less (SHA-less) architecture was preferred since the SHA was one of the most power-consuming sub-blocks, and brought inevitable noise and distortion. A composite ADC architecture, having 8x 1.5-b cascaded stages and a back-end 3-b flash ADC is designed to reach up to 11-b physical resolution. A novel MDAC is proposed to mitigate ISI. Moreover, a novel BiCMOS residue amplifier (RA), which performs 6.43 GHz UGB and 80 dB DC gain, is implemented. A non-overlapping clock generation architecture at 1.6 GHz is devised, incorporating a differential clock driver and clock level converters.The SNRjitter of the clock generation system is 57 dBc at a clock signal frequency of 1.6 GHz. The results of the measurements carried out at ITU VLSI are included in the thesis. SiGe BiCMOS 0.13 μm process is utilized to fabricate the complete ADC, which has a 1.6 V supply and a silicon area of 2.2 mm × 3 mm.