A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices
A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices
dc.contributor.author | Aksoy, Levent | |
dc.contributor.author | Altun, Mustafa | |
dc.contributor.department | Elektronik ve Haberleşme Mühendisliği | tr_TR |
dc.contributor.department | Electronics and Communication Engineering | en_US |
dc.date.accessioned | 2019-05-20T14:05:31Z | |
dc.date.available | 2019-05-20T14:05:31Z | |
dc.date.issued | 2019 | |
dc.description.abstract | In recent years the realization of a logic function on two-dimensional arrays of four-terminal switches, called switching lattices, has attracted considerable interest. Exact and approximate methods have been proposed for the problem of synthesizing Boolean functions on switching lattices with minimum size, called lattice synthesis (LS) problem. However, the exact method can only handle relatively small instances and the approximate methods may find solutions that are far from the optimum. This paper introduces an approximate algorithm, called JANUS, that formalizes the problem of realizing a logic function on a given lattice, called lattice mapping (LM) problem, as a satisfiability problem and explores the search space of the LS problem in a dichotomic search manner, solving LM problems for possible lattice candidates. This paper also presents three methods to improve the initial upper bound and an efficient way to realize multiple logic functions on a single lattice. Experimental results show that JANUS can find solutions very close to the minimum in a reasonable time and obtain better results than the existing approximate methods. The solutions of JANUS can also be better than those of the exact method, which cannot be determined to be optimal due to the given time limit, where the maximum gain on the number of switches reaches up to 25%. | tr_TR |
dc.description.sponsorship | This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178, and supported by the TUBITAK-Career project #113E760 | en_US |
dc.identifier.citation | L. Aksoy and M. Altun, "A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices," 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, 2019, pp. 1637-1642. doi: 10.23919/DATE.2019.8714809 | en_US |
dc.identifier.uri | http://hdl.handle.net/11527/18005 | |
dc.identifier.uri | doi: 10.23919/DATE.2019.8714809 | |
dc.language.iso | en | tr_TR |
dc.publisher | IEEE | tr_TR |
dc.relation | Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer | en_US |
dc.relation | NANOxCOMP | en_US |
dc.relation | 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) | en_US |
dc.relation.ispartofseries | Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer (NANOxCOMP) | en_US |
dc.source.uri | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8714809&isnumber=8714721 | |
dc.subject | Logic synthesis | en_US |
dc.subject | Mantık sentezi | tr_TR |
dc.subject | Anahtarlama kafesleri | tr_TR |
dc.subject | Switching lattices | en_US |
dc.title | A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices | en_US |
dc.type | Presentation | en_US |
dc.type | Conference Paper | en_US |
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