Programlanabilir lojik kontrolörler için tasarım yöntemleri

Abstract

Bu tezde, endüstriyel otomasyon ve kontrol sistemleri için geliştirilmiş olan programlanabilir lojik kontrolörlerde (PLC), kumanda devrelerinin tasarım yöntemleri incelenmiştir. Bölüm 1, programlanabilir lojik kontrolörler hakkında genel bilgiler içermektedir. Ayrıca, bu bölümde, PLC'lerin gelişimi ve iç yapısı anlatılmaktadır. Bölüm 2'de, PLC'lerde kullanılan işletim sistemleri hakkında genel bilgi verilmiş, PLC'lerde programlama yöntemleri incelenmiş ve geleneksel bir kumanda devresinin PLC'lerde gerçeklenebilmesi için gerekli PLC komutları anlatılmıştır. Bölüm 3'te, kömbinezonsal ya da asenkron ardışıl devre yapısında olan kumanda devreleri için lojik devre tasarım yöntemleri incelenmiştir. Asenkron ardışıl devre yapısmda olan kumanda devrelerindeki iç durum kodlanması sorununa çözüm önerileri sunulmuştur. Bölüm 4'te, kumanda devrelerinin doğrudan merdiven diyagramı şeklinde tasarlanarak PLC'ye aktarılması için bir yöntem verilmiştir.

Programmable logic controllers are special proposed digital controller or industrial computers which are developed for automation and control systems. Although the first usage area of these devices were industrial automation systems, nowadays they can be used either in command circuits or feedback control circuits in an industrial plant The first commercial PLC was developed by Modicon company in 1969. In those years this device which was developed for replacement of relay command circuits was called programmable logic controller (PLC), because they could be used to realize basic logical functions. Firstly after succesfuHy implementations of the PLC's in industry, companies such as Allen-Bradley, General Electric, GEC, Siemens and Westinghouse produced middle priced, high performanced PLC's. Then, companies like Mitsubishi, Omron and Toshiba developed low cost high performanced PLC's, and so these devices began to be used widely in industry. The controllers produced nowadays, can perform arithmetic and special mathematical functions, in addition to basic logic functions, and so they can overcome more complicated command and control functions. Most PLC's have utility programs and functions that are widely used in control circuits instead of PID controllers. The structure of a PLC is illustrated in fig 1. A PLC consists of; - A microcomputer (microprocessor + memory + input-output interface) or microcontrollers. - Input-output units. - Programmer unit - Power supply unit Additionally, it also contains EEPROM module for backing up program and for transfering the program to another PLC, an expansion unit for increasing input- output units and in case of power failure, uninterruptable power supply (UPS) and special comminications interface adaptor. Button, sensors,mechanic contact ! XIIIZIX"' [^^^^Inputunit^^^^J un _*_:: Input image register ( lbit) fl Comminicationpath Central Processing Unit ] * Output image regjter (1 bit) ' ; ; | ; ; jr. _r :' Memory 1 I Output unit I '.İ.1İ.İ.I.İ...İ..... Contoktor, mohv, selonoid Figure 1. The structure of a PLC The realization of industrial command circuits by using PLC's consists of two steps; L The design of logic functions or relay command circuits to solve common problems. ii. The programming of obtained logic functions or relay command circuit and loading the PLC. Conventional command circuits consists of subcircuits which have the structure of either combinational circuit or asynchronous sequentional circuit Before designing the command circuit, one must specify the structure of the circuit which accomplish the desired command function. The particular characteristic of a combinational circuit is that its outputs are functions of only the present circuit inputs. The realization of the combinational circuits with PLC has two steps; i. The problem is stated and the number of available input variables and required output variables is determined. The tram table that defines the required relationships between inputs and outputs is derived. ii. The simplified Boolean function for each output is obtained. VI An asynchronous sequential circuit quite often resembles a combinational circuit with feedback. The outputs of the circuits are specified by the input sequences. The realization of the asynchronous sequential circuits with PLC has five steps. i. A primitive flow table is constructed from the verbal description of the circuit operation. ii. A minimum-row reduced flow table is obtained by merging the rows in the primitive flow table. iii. Each row of the reduced flow table is assigned binary state variables. The procudure of state assignment that eliminates any possible critical races. iv. Excitation and output tables are constructed. The outputs associated with the unstable states are specified according to the various design requirements. v. The excitation and output functions are derived, and corresponding ladder diagram or statement list is designed. The internal state of an asynchronous sequential circuit (ASC) can be represented by an n-digit binary data word y. State transitions occur in response to changes in the ASC's input state. Let ya and yp represent the present and next states, respectively. The Hamming distance Hd between ya and yp is denned as the number of digit position in which the corresponding digits of ytt and yp are different If Hd > 0, a state transition occurs since ya * yp. During the time interval that the state is switching from y0 and yp, one or more digits in y become unstable; that is, their actual state at any instant in time is not known. However, a potential problem may occur if more than one digit in y becomes unstable at any instant in time. This condition, known as a race, occurs when Hd > 1. A race can be either critical or noncriticaL Critical races may cause an ASC to malfunction because the next state might depend on the order in which the unstable digits in y change state. In chapter III, a state assignment technique is introduced for synthesizing asynchronous sequential logic circuits. It provides a systematic and efficient approach for generating race-free state assignments. A race condition is classified as being either an intrinsic race (ER) or a generated race. Intrinsic races decompose into two subclassifications: visible intrinsic races and hidden intrinsic races. A graph, referred to as a Node-Weight Diagram, facilitates the process of making state assignments and quarantees that no races are generated. Moreover, it provides a convenient and efficient method for investigating the implications of selecting from an allowed set of alternative race-free state assignments. The state assignment technique described adds cycles and states, as needed, to avoid IR's and always attemps to use the minimum or near-minimum number of state variables and states. vn This technique has been implemented and incorporated into an ASC design automation system. Experimental results show that it provides significantly better results then other approaches in terms of the computation time required to make the assignments and the number of state variables required to achieve race-free ASC. In chapter TV, a method for designing ladder diagrams for seqencing tasks is described. It is systematic, fast, and simple to apply. The methods divides the required sequence into groups according to a simple rule. These groups are then encoded using the "one-hot" code, with each group assigned one relay operating as flip-flop. The method can also be adapted to sysyems with multi-path sequences having one or more random inputs. This is important with simple, low-cost PLCs, having no provisions for conditional jumps. Four examples of such multi-path sequences are presented in chapter iv. The practical requriments become completely different the moment it is decided to implement the ladder diagram by means of PLCs, rather than with hard wired relays. Programmable logic controllers imitate relay action through software. Thus once the PLC has been purchased, the "relays" cost nothing, and the relay capacity of even small PLCs is fairly large, so that there is no point in making a great effort to save a relay or two. What is important is that the design method be fast and simple, and the resulting ladder easily understood. In spite of the above, a simple, economical ladder diagram will usually be preferable, even when using PLCs. The reasons are given below. i. If a small, low-cost controller is used for a problem of medium complexity, it is easy to run out of memory. A simple ladder diagram uses less memory. it A simple diagram is usually easier to understand, to check, to troubleshoot and to modify, and to modify, and it takes less time to enter it into the controller's memory. iii. With many PLCs, the scanning time depends on the amount of memory used. Thus, the controller will respond faster if the program is kept as short as possible. In the method to be described in chapter iv, the varios steps of te program sequence are divided into groups according to the following principle: A new group must be started the moment it becomes necessary to shut off any output signal actuated during the presently-active group in order to prevent simultaneous actuation of opposing selenoids. In other words, any output signal actuated is permitted to remain so as long as the group it belongs to is active. vm To abide by this principle, the necessary design procedure can be summarized as follows. i. Divide the steps of the program sequence into groups according to the above principle. ii. To each group, assign one relay connected to implement a set-reset flip-flop. a) The first flip-flop is SET by the START signal b) All other Flip-flops are SET by a sensor signal indicating completion of the last step of the previous group. c) The last flip-flop is RESET by a sensor signal indicating completion of the last group. d) All other flip-flops are RESET by a normally-closed contact of the succeeding relay. iii. Draw a ladder-diagram rung for each output signal, with a number of parallel lines equal to the number of groups in which that output signal must be activated. a)If the output is to be ON during the entire group, insert a normally-open contact of the relay assigned to that particular group into the line. b)If the output is to turn ON while the group is active, proceed as in (a), but connect the relay contact in series with a sensor contact which will close when the output is required to go ON.