RISC-V processor design for secure communication applications

Abstract

The performance of a processing unit increases every year with the technological advances and architectural approaches. Although the performance increases, repeated long-latency operations cause performance degradation and, at the end, the overall performance of a processor degrades. As an architectural improvement, an accelerator can be designed for a specific task and integrated to processing unit. Therefore, stalls can be eliminated and performance degradation can be prevented. There are applications which comprise communicating devices. These devices can deploy encrypted messages over a long range communication channel. Therefore, the application requires to implement cryptography algorithms and modulation schemes. Cryptography algorithms provide secure communication on insecure channels. These algorithms aim to provide confidentiality, authentication, and data integrity. To achieve these goals, they comprise mathematical operations that prevent unintended device to access shared information. Encrypted messages are digital signals which are not suitable for wireless communication. Therefore, modulation schemes are employed to convert digital signals into signals which are bandwidth and power efficient. Modulation schemes utilize carrier signals which have varying features according to message. A general purpose processor allows to run software. A software is converted into instructions and each instruction executed on the processor. In-order processors fetch the instructions as they are ordered by compiler. Instructions define the operation such as memory, arithmetic, and control flow. The memory and arithmetic operations can last more than one clock cycle depending on the function of the instructions. When these instructions are fetched they stall the pipeline due to structural or data hazards. The pipeline can also stalls if an instruction uses the same register with the earlier instruction. These stalls degrade the performance of a sequential core. The cryptography algorithms comprise mathematical functions for encryption and decryption. The modular exponentiation and bitwise operations are 2 of these functions. A modular exponentiation is converted into multiplication and division instructions which cause stalls on the pipeline. Cryptography algorithms can comprise repeated number of bitwise operations. Since most of them can be processed parallel, sequential processing is not efficient. Therefore, an accelerator can be integrated to a processor to prevent performance degradation. The modulation schemes utilize sinusoidal signals to modulate messages. These signals can be generated with Taylor's Series. The Taylor's Series calculates the trigonometric functions with arithmetic operations such as multiplication and division. Yet, multiplication and division instructions can cause stalls in in-order processors. Therefore, Taylor's Series calculations cause stalls on the processor and degrades the performance. The performance degradation caused by modulation schemes can be prevented with an accelerator. In this thesis, a processor with 2 custom functional units is designed for secure communication applications. The processor is a 3 stage, in-order, RISC-V processor. The functional units are designed to perform calculations of cryptography algorithms and modulator schemes. The Diffie-Hellman Key Exchange (DHKE) protocol is implemented to share secret key. The Rivest Shamir Adleman (RSA) algorithm is implemented to provide authentication. The confidentiality can be established by using Advance Encryption Standard (AES) block cipher in Cipher Block Chaining (CBC) mode. The Cipher based Message Authentication Code (CMAC) or Secure Hash Algorithm (SHA) algorithms can be used to calculate hash value of any data. The modulator unit can be reconfigured on run time without any configuration data. With modulator unit, messages can be modulated with one of Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), Minimum Shift Keying (MSK), and Gaussian Minimum Shift Keying (GMSK) schemes. The instruction set of the processor is extended to control custom functional units. To observe the speedup provided by these units, a message is encrypted with AES block cipher and cipher text is modulated with QPSK scheme. A default 3-stage, RISC-V processor and designed processor is simulated and their simulation result is compared. The simulation results show that the designed processor provides 16x speedup. Therefore, the delay between encryption and modulation of 2 consequent messages is reduced. So that, a general purpose processor suitable for secure communication applications is achieved. As the result, designed processor can be used in that applications with its benefits such as ease of development.