Low power general purpose processor design and instructions set extension for AES

Abstract

In the last years, there has been a big growth in the demand for portable electronic devices. Most of these devices need to operate on a thrifty energy budget and they must be designed to work under extreme energy constraints for a long time. Also, a lot of smart devices need to communicate with the outer world and with other devices, and all these communications must be secure. These requirements have increased the investments in developing low-power integrated circuits with encryption capabilities. In this thesis, a low-power general purpose processor design is presented. Then the processor design is improved by extending the instruction set with instructions for the Advanced Encryption Standard (AES). In chapter one, many embedded systems architectures for low-power applications are introduced, then in chapter two the Advanced Encryption Standard is explained. In chapter four, the designed processor's instruction set is given, and its architecture is explained in detail. Then the processor architecture is improved by adding many pipeline stages. Pipeline hazards are handled without complicating the processor architecture. In chapter five, both processor designs (the non-pipelined and the pipelined) were tested with simple programs to compare its performances. The pipelined processor showed better results in terms of the required clock cycles to finish test programs, the throughput and the consumed energy. Both processor designs were also compared with the well-known Xilinx PicoBlaze processor. The pipelined processor beat PicoBlaze according to the maximum clock rate and dynamic on chip power. In chapter six, The AES algorithm is implemented in Assembly language and is run on the pipelined processor. Then AES algorithm code is investigated using its control flow graphs.