Pıpelıne Adc Tasarımı

Abstract

Baz istasyonlarına pek çok kullanıcıdan gelen geniş bantlı işaret, boru hattı tipi (pipeline) analog sayısal dönüştürücüler (ADC) vasıtası ile sayısala çevrilir. Bu çalışmada, 12 bit çözünürlükte ve 20 Mhz örnekleme frakansındaki bir pipeline ADC’nin şematik tasarımı ve benzetimleri yapılmıştır. Transistör bazında tasarıma geçilmeden önce, mimarinin modellemesi yapılmış ve daha sonra bu modeller benzetim ortamına da taşınmıştır. Benzetim ortamındaki modellerin hatasız çalıştığı gözlendikten sonra transistör temelli tasarıma geçilmiştir. Tasarımda, standart bir 0.18µ CMOS prosesin 3.3V gerilime dayanıklı transistörleri ve BSIM 3.3 modelleri kullanılmıştır. Analog devrelerin ve sayısal kapıların şema tasarımlarının ve birarada (mix-mode) benzetimlerinin yapılabilmesi için, LTSPICE-IV ücretsiz yazılımı kullanılmıştır. Tasarım, davranışsal mantık kapıları içermesi haricinde, transistör seviyesinde ve tam farksal olarak yapılmıştır. Besleme gerilimi 3.3 volt, giriş işareti tepeden tepeye farksal 0.8 volt, ve ortak mod ise 1.6 volt olarak seçilmiştir. Tasarım 395 mW güç harcar ve 21 MHz giriş işareti için, 84 dB dallarından arındırılmış hareketli aralık (spurious free dynamic range, SFDR) başarımına sahiptir. Toplam güç harcamasının azaltılabilmesi için, boru hattı katlarının, kat numarası arttıkça daha az güç harcayan bloklardan oluşmasına dikkat edilmiştir. SFDR başarımını arttırmak için ise, önyükleyicili anahtar (bootstrapped switch) mimarisi kullanılmıştır. Teorik hesaplar sonucunda 71.3 dB işaret gürültü oranı (SNR) beklenmektedir. Bu gürültü, kuantalama gürültüsünün az bir miktar üzerindedir. Gürültünün düşük seviyede tutulabilmesi için işlemsel kuvvetlendirici gürültüsünün ve kT/C gürültüsünün azaltılmasına özen gösterilmiştir. Giriş band genişliği 200 MHz mertebesinde olup, alt örnekleme (undersampling) uygulamalarına müsaittir. Örnekleme hızı, tam başarımda 20 MHz olup, başarımın bir miktar düşmesi göze alınırsa 40 MHz mertebesine kadar çıkabilir. İdeal benzeşme durumunda, +/- 0.25 en az önemde ikilik rakam (least significant bit, LSB) tümlevsel doğrusallık hatası (Integral Nonlinearity Error, INL) elde edilmiş, ve transfer fonksiyonunun doğruluğu tüm entegre için INL ölçümü ile gösterilmiştir. Boru hattı tipi ADC’nin SFDR benzetimi, LTSPICE-IV ortamında, davranışsal modeller kullanılarak dakikalar mertebesinde tamamlanmaktadır. Tasarımın 128 sayısal çıkıştan oluşan transistör temelli SFDR benzetimleri ise, i5 işlemcili 2.5 GHz hızında bir dizüstü bilgisayarda 16 saat mertebesinde tamamlanmaktadır. Akşamdan benzetim koşturup sabah sonuçları almak mümkündür. Kod sayısı düşürülerek süre kısaltılabilir. Boru hattı analog sayısal dönüştürücüsü gibi karmaşık bir analog entegre devrenin, ücretsiz bir yazılım ortamı ve dizüstü bilgisayar kullanarak “evde” tasarlanabileceğini göstermesi açısından, bu çalışma elektronik eğitiminde ve geleceğin genç analog tasarım meraklılarının yetiştirilmesinde ek önem taşımaktadır.

Multi-user, wideband signals that arrive to cellular base station receivers are converted to digital using pipeline analog to digital converters (ADCs). In this work, schematic design and circuit simulations of a 12 bit 20 MHz pipeline ADC is presented. A Matlab model of the ADC is first constructed, followed by a behavioral SPICE model. After flawless operation is observed from both models, transistor level schematic design begins. In the schematic design, 3.3V capable transistors of a 0.18µ CMOS process are used with BSIM 3.3 Mosfet models. To do the schematic design and mixed-mode simulation of the analog circuits with digital gates, a freeware electronic design automation (EDA) environment, LTSPICE-IV is used. Apart from behavioral logic gates which are used to speed up the simulations, the design is fully differential at transistor level. The supply voltage is 3.3 volts, and the input signal amplitude is 0.8 volt peak-to-peak differential around a 1.6 volt common mode. The simulations show 84 dB spurious free dynamic range for a 21 MHz input signal, with 395 mW power consumption at 20 Msps. The power consumption of the logic blocks are not included in 395 mW, but their actual contribution to power consumption should be insignificant. To reduce power consumption, scaling of the stages, which includes the interstage sampling capacitors and sample and hold amplifiers, is used. To increase the SFDR at higher input frequencies, bootstrapped input switches at the sample and hold are used. As a result of amplifier noise simulations and kT/C calculations, 71.3 dB signal to noise ratio is expected. The analog input bandwidth is around 200 MHz and the design is suitable for undersampling applications. Assuming perfect matching, the integral nonlinearity error is measured as +/- 0.25 LSBs, and the integrity of the transfer function is proven using linearity simulations. The SFDR simulations of the pipeline ADC’s behavioral LTSPICE model are completed within a few minutes. Using fully accurate (slowest) simulator settings, transistor level SFDR simulations using 128 ADC output codes take approximately 15 hours on a low end laptop computer using a 2.5 Ghz Intel i5 processor with 6 Giga bytes of RAM. While we demonstrate that full chip 128 code SFDR simulations can be completed overnight, we would like to point out that less number of codes can be used to get SFDR results quicker. This work shows that a complicated mixed signal design such as a pipline ADC can be done “at home” using today’s personal computers and freeware EDA tools. In this sense, this work has additional value in electronic design education and in motivating young analog IC design enthusiasts of the future. Digital signal processing applications are widely used in our life. Especially, digital signal porcessing takes a very important place in communication systems and it can be said that there is no alternative to using digital signal processing in digital communications. Digital signal processing can be described as, converting analog signal to digital domain, analyzing the digital outputs using a digital signal processor and converting the digital results back to analog domain. Analog signals are transformed to digital data with analog to digital converters. Opposite transformation is realized by digital to analog converters. High performance applications need high performance converters. It can be said that the performance of certain applications can be determined only by the performance of converters. Although the performance of digital signal processors is adequate, converter technology is playing catch-up. Two types of converte performance criteria are defined in literature. One is static performance and the other is dynamic performance. In addition to these criteria, a figure of merit is used to indicate the performance of converter per unit power consumed. The first goal of many studies is to get more effective number of bits and conversions per second with less power. Static performance parameters are used to define DC errors of the converter. Main purpose of these parameters is to determine the difference between actual output with the ideal output. These parameters provide boundary information about offset, gain, differential nonlinearity (DNL), integral nonlinearity (INL) and missing codes errors. DC errors also effect AC performance. For instance, DC nonlinearity can cause harmonic distortion at the output. Missing codes can cause discontinuities at the output. Dynamic performance parameters are used to define AC errors of converter. These errors are defined for different frequency spans and values. AC characteristics are usually frequency related.These parameters are very important for certain applications . For example, bandwidth requirement of a DSL modem is different from the bandwidth requirement of a base station. AC characteristics of converters become increasingly important in communication applications such modulation, demodulation etc. Signal to noise ratio (SNR), total harmonic distortion (THD), spurious free dynamic range (SFDR) and analog input bandwidth (BW) are among important dynamic performance parameters. The most important parameters for an ADC are sample rate and bit resolution. These parameters differ among several architectures. For example, if more accuracy and resolution are needed, SAR and Delta Sigma architectures are used. But they have a handicap. They can’t reach high sample rates. If high sample rates are desired, comparator based Flash ADCs are used. Although flash converters are fast, their accuracy is limited to 5 to 8 bits. So, newarchitectures are needed to simultaneously optimize speed and accuracy. The pipelined ADC architecture is a good architecture in terms of speed and accuracy. If the start up delay (the elapsed time till pipeline fills) is ignored, the speed of the pipeline ADC is the same as a flash ADC. . In addition, bit resolution of a pipeline ADC is higher than a flash ADC and is adequate for many applications. A basic pipeline converter consists of an input sample and hold stage, a pipeline core, and a digital error correction block. The input signal is sampled by the input sample and hold stage and the result is transferred to the pipeline core. This core consists of serial connected sub converter blocks, where each block can resolve certain number of bits. Fundamental operation is based on long division. The data which is resolved at the first stage is reproduced and subtracted from the input signal of the block. Finally the remainder of the subtracted signal is multiplied by two and transferred to next block. If these operations are considered mathematically, it is a binary division. Multipliying by two is the same as digit shifting in the division operation. Also remaining signal is called residue. So, each block resolves the signal, makes a coarse division, subtracts the resolved signal from the input signal, and transfers the residue to next block for finer divisions. A notable innovation in pipeline ADC architecture is the insensitivity to comparator offset errors using a technique called digital error correction. This algorithm is based on Redundant Signed Digit presentation. The data produced from unit blocks have to be time aligned. There is a delay between stages because of the analog pipeline. Conversions of unit blocks are similarly aligned with digital delay elements. Digital error correction operation becomes a simple summing operation at the end of the time alignment.The SFDR performance of the design is determined by the performance of input sample and hold amplifier. Noise level, input bandwith, SFDR and most of DC errors are mostly determined by this stage. So input sample and hold stage has to be designed to have low noise, fast settling, and high accuracy Most of sample and hold stage AC errors are caused by the input sampling switch nonlinearity. It is known that resistance of mos switch depends on gate-source voltage. When switch gate node is tied to a supply and the source node is tied to the input, resistance of switch depends on input voltage. This causes input dependent RC time constants, which result in nonlinear behavior for high frequency inputs. To overcome this limitation, bootstrapped switches are used at the input. Bootstrapping provides constant gate-source voltage and resistance of switches becomes independent of the input signal. Another important issue is the performance of amplifiers. Settling accuracy of the amplifiers limit the effective number of bits of the ADC and the settling time of the amplifier limit the sampling rate of the ADC. The amplifiers should settle well within half the clock period and settling accuracy must be within a fraction of an LSB. Thanks to the digital error correction algorithm, comparator offsets are not a limitation. If an error occurs, it is corrected by following stages. Clocking scheme is as important as block performance. Rise and fall times have to be as short as possible to improve speed and to reduce jitter. To eliminate possible charge injection and other common mode effects, a fully differential architecture is used. Bottom plate sampling is used in the input stage to help reduce charge injection from input switches. Power consumption is one of the important performance parameters of ADCs. Today, most electronic devices are powered by low voltage sources, especially batteries. . To consume less power, stage scaling is applied, assensivity to accuracy is divided in progressive blocks. For example, the error of the third stage will effect the output by one-fourth of the effect of the first stage . So the consecutive stages don’t have to be as precise as the previous blocks. Power consumption of all stages are reduced using this method.