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A Novel Reversible Fault Tolerant Microprocessor Design In Ams 0.35Um Process

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dc.contributor.authorCilasun, M. Husrev
dc.contributor.authorAltun, Mustafa
dc.date.accessioned2026-01-31T11:42:52Z
dc.date.issued2017-01-01
dc.description.abstractIn this study, reversible circuits are revisited to achieve extreme soft-defect awareness in classical CMOS circuits. Defect models in the literature are reviewed and defect scattering is analyzed. A reversible 8-bit full adder is designed in 12-bit block code domain. As a proof of concept, a pair of reversible ALUs are embedded into a microprocessor with block-code encoded data-path. The design is simulated in ams 0.35um process and a layout is obtained for tapeout.
dc.description.urihttps://aperta.ulakbim.gov.tr/record/50187
dc.identifier.openairer39c86a4b39b::3d2cf7f03b9949430210aebea91e6d32
dc.identifier.urihttps://hdl.handle.net/11527/70697
dc.publisherAperta
dc.rightsOPEN
dc.titleA Novel Reversible Fault Tolerant Microprocessor Design In Ams 0.35Um Process
dc.typeOther
dspace.entity.typePublication

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