Excess Capacitance Due to Minority Carrier Injection in CrSi2/p-Type Crystalline Si Isotype Junction

Abstract

Excess current and capacitance phenonema were observed for the first time on a CrSi2/p-type crystalline silicon junction produced by cathodic arc physical vapor deposition. The heterojunction was investigated by current–voltage–temperature (I–V–T) and capacitance (conductance)–voltage/temperature (C,G–V/T) measurements for the purpose of studying transport and storage features. Excess current, manifested as a crossover at a large forward bias, was observed in I–V–T curves since minority carriers injected into the quasi-neutral region of p-c-Si were neutralized by majority carriers supplied from the p-c-Si semiconductor side. This phenomenon, known as conductivity modulation, appeared distinctly as a hump in C–V/T curves (storage property); a sharp rise in capacitance towards a maximum value as forward bias increased and the subsequent fall after a specific value. For reverse and low forward bias regions, where minority carrier injection was negligible, geometrical junction capacitance and a shoulder in C–V/T curves were observed. In the voltage range where the peak was observed in C–V/T measurements, trap-assisted tunneling recombination generation and space-charge-limited current (SCLC) mechanisms were determined in the CrSi2/p-c-Si isotype junction. Traps introduced during tunneling were identified as bulk point defects due to the chromium–boron (Cr–B) complex for the CrSi2/p-c-Si junction on the Si side by I–V–T and C(G)–T analyses. This finding seemed to be in agreement with a recent DLTS [Deep Level Transient Spectroscopy] measurement in terms of both energy depth (0.26 eV) and bulk nature. Finally, the shoulder in C–V/T curves indicated Cr–B point defects in the measurement.