Statistical design techniques for yield enhancement of low voltage CMOS VLSI

Abstract

Since random device/process variations do not scale down with feature size or supply voltage, statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. This is particularly true for low voltage analog ICs. This paper presents a robust design of a low voltage square-law CMOS composite cell, using statistical VLSI design tools. The Response Surface Methodology and Design of Experiment techniques were used as statistical tools. This paper shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.