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Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU

dc.contributor.authorClarke, Ryan
dc.contributor.authorJacob, Philip
dc.contributor.authorErdogan, Okan
dc.contributor.authorBelemijian, Paul
dc.contributor.authorRaman, Srikumar
dc.contributor.authorLeroy, Mitchell R.
dc.contributor.authorNeogi, Tuhin Guha
dc.contributor.authorKraft, Russell P.
dc.contributor.authorBorca-Tasciuc, Diana-Andra
dc.contributor.authorMcdonald, John F.
dc.date.accessioned2026-01-26T02:09:28Z
dc.date.issued2015-01-01
dc.description.abstractWe have previously evaluated the feasibility of a serial code accelerator core with 3-D DRAM stacked on the core operating at high frequencies. While operating at such high frequencies (>24 GHz), there are concerns with removing heat from the 3-D stack. We propose the use of thin diamond sheets, which have high thermal conductivity, as a heat spreader by bonding it close to the processor core substrate and memory stacks. We show, through thermal modeling using COMSOL finite-element analysis tools, the feasibility of diamond as an effective heat spreader in a processor-memory 3-D stack.
dc.description.urihttps://doi.org/10.1109/access.2015.2396474
dc.description.urihttps://doi.org/10.1109/ACCESS.2015.2396474
dc.description.urihttps://doaj.org/article/0e37535f0afa4f08ab5422b299d0d98f
dc.description.urihttps://dx.doi.org/10.1109/access.2015.2396474
dc.identifier.doi10.1109/access.2015.2396474
dc.identifier.eissn2169-3536
dc.identifier.endpage54
dc.identifier.openairedoi_dedup___::c26a6e2ef08c942d5bb52078754d5c6a
dc.identifier.startpage43
dc.identifier.urihttps://hdl.handle.net/11527/56984
dc.identifier.volume3
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.relation.ispartofIEEE Access
dc.rightsOPEN
dc.sdg.typeGoal 7: Affordable and Clean Energy
dc.subjectmemory
dc.subjectMoore’s law
dc.subjectmodeling
dc.subjectElectrical engineering. Electronics. Nuclear engineering
dc.subjectsimulation
dc.subjectD IC
dc.subjectMicroprocessors
dc.subjectTK1-9971
dc.titleThermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU
dc.typeArticle
dspace.entity.typePublication

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