A new neuron and synapse model suitable for low power VLSI implementation

Abstract

A new dynamical neuron model for low power and compact VLSI implementation is presented. The model is capable of generating the most common type of spiking patterns. Judicious use of subthreshold CMOS design techniques leads to a very effective low-power CMOS Neuron and synapse circuits. The circuit consists of a single first-order log domain filter and a few hyperbolic function generators. We have also developed a circuit which realizes the synaptic interconnections of the neurons. Based on this complete neuron and synapse model, we studied synchronization behavior of two reciprocally interconnected neurons with excitatory and inhibitory couplings. Owing to the use of log-domain design and current-mode design, the circuits occupying low chip area and having very low power consumption are obtained even at real biological time-scale operation. These features make these circuits especially suitable for hybrid interface applications and large scale VLSI neuromorphic networks.