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ÖgeComputing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance(IEEE, 2017) Altun, Mustafa ; Ciriani, Valentina ; Tahoori, Mehdi ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication EngineeringNano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and can be fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, our project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. First two work packages of the project are presented in this paper. These packages are on logic synthesis that aims to implement Boolean functions with nanocrossbar arrays with area optimization, and fault tolerance that aims to provide a full methodology in the presence of high fault densities and extreme parametric variations in nano-crossbar architectures.
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ÖgeDefect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation(IEEE, 2018) Tunali, Onur ; Morgül, M. Ceylan ; Altun, Mustafa ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication EngineeringIn this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs.
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ÖgeA Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays(IEEE, 2018) Peker, Furkan ; Altun, Mustafa ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication EngineeringNano-crossbar arrays are area and power efficient structures, generally realized with self-assembly based bottom-up fabrication methods as opposed to relatively costly traditional top-down lithography techniques. This advantage comes with a price: very high process variations. In this work, we focus on the worst-case delay optimization problem in the presence of high process variations. As a variation tolerant logic mapping scheme, a fast hill climbing algorithm is proposed; it offers similar or better delay improvements with much smaller runtimes compared to the methods in the literature. Our algorithm first performs a reducing operation for the crossbar motivated by the fact that the whole crossbar is not necessarily needed for the problem. This significantly decreases the computational load up to 72% percent for benchmark functions. Next, initial column mapping is applied. After the first two steps that can be considered as preparatory, the algorithm proceeds to the last step of hill climbing row search with column reordering where optimization for variation tolerance is performed. As an extension to this work, we directly apply our hill climbing algorithm on defective arrays to perform both defect and variation tolerance. Again, simulation results approve the speed of our algorithm, up to 600 times higher compared to the related algorithms in the literature without sacrificing defect and variation tolerance performance.
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ÖgeIntegrated Synthesis Methodology for Crossbar Arrays(IEEE, 2018) Morgul, M. Ceylan ; Frontini, Luca ; Tunali, Onur ; Vatajelu, E. Ioana ; Ciriani, Valentina ; Anghel, Lorena ; Moritz, Csaba Andras ; Stan, Mircea R. ; Alexandrescu, Dan ; Altun, Mustafa ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication EngineeringNano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.
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ÖgeLogic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays(Elsevier, 2017) Alexandrescua, Dan ; Altun, Mustafa ; Anghel, Lorena ; Bernasconi, Anna ; Cirianie, Valentina ; Frontini, Luca ; Tahoori, Mehdi ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication EngineeringBeyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of “Emerging Computing Models” or “Computational Nanoelectronics”, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS.
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ÖgeOptimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches(Elsevier, 2019) Morgul, M. Ceylan ; Altun, Mustafa ; Electronics and Communication Engineering ; Elektronik ve Haberleşme MühendisliğiIn this work, we study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a fourterminal switch controlled by a Boolean literal. These types of arrays are commonly called as switching lattices. We propose optimal and heuristic algorithms that minimize lattice sizes to implement a given Boolean function. The algorithms are mainly constructed on a technique that finds Boolean functions of lattices having independent inputs. This technique works recursively by using transition matrices representing columns and rows of the lattice. It performs symbolic manipulation of Boolean literals as opposed to using truth tables that allows us to successfully find Boolean functions having up to 81 variables corresponding to a 9×9-lattice. With a Boolean function of a certain sized lattice, we check if a given function can be implemented with this lattice size by defining the problem as a satisfiability problem. This process is repeated until a desired solution is found. Additionally, we fix the previously proposed algorithm that is claimed to be optimal. The fixed version guarantees optimal sizes. Finally, we perform synthesis trials on standard benchmark circuits to evaluate the proposed algorithms by considering lattice sizes and runtimes in comparison with the recently proposed three algorithms.
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ÖgeRealization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling(IEEE, 2019) Safaltin, Serzat ; Gencer, Oguz ; Morgul, M. Ceylan ; Aksoy, Levent ; Gurmen, Sebahattin ; Moritz, Csaba Andras ; Altun, Mustafa ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication Engineering ; Metallurgical and Materials Engineering ; Nanoscience and NanoengineeringOur European Union’s Horizon-2020 project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Within the project, we investigate different computing models based on either two-terminal switches, realized with field effect transistors, resistive and diode devices, or four-terminal switches. Although a four-terminal switch based model offers a significant area advantage, its realization at the technology level needs further justifications and raises a number of questions about its feasibility. In this study, we answer these questions. First, by using three dimensional technology computer-aided design (TCAD) simulations, we show that four-terminal switches can be directly implemented with the CMOS technology. For this purpose, we try different semiconductor gate materials in different formations of geometric shapes. Then, by fitting the TCAD simulation data to the standard CMOS current-voltage equations, we develop a Spice model of a four-terminal switch. Finally, we successfully perform Spice circuit simulations on four-terminal switches with different sizes. As a follow-up work within the project, we will proceed to the fabrication step.
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ÖgeSensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs(Elsevier, 2019) Atasoyu, Mesut ; Altun, Mustafa ; Ozoguz, Serdar ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication EngineeringIn this work, we investigated the sensing challenges of spin-transfer torque MRAMs structured with perpendicular magnetic tunnel junctions with a high tunneling magnetoresistance ratio in a low resistance-area product. To overcome the problems of reading this type of memory, we have proposed a voltage sensing amplifier topology and compared its performance to that of the current sensing amplifier in terms of power, speed, and bit error rate performance. We have verified that the proposed sensing scheme offers a substantial improvement in bit-error-rate performance. To enumerate the read operations of the proposed sensing scheme with the proposed cross-coupled capacitive feedback technique on the clamped circuity have successfully been performed a 2.5X reduction in average low power and a 13X increase in average reading speed compared with the previous works due to its device structure and the proposed circuit technique.
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ÖgeSpin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers(IEEE, 2017) Atasoyu, Mesut ; Altun, Mustafa ; Ozoguz, Serdar ; Roy, Kaushik ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication EngineeringUnpredictable threshold voltage changes of CMOS transistors cause input referred random offset (IRRO) in sense amplifiers. With the shrinkage of transistors in nano regime, it is being quite costly to cancel the offsets using conventional CMOS based techniques. Motivated by this fact, this study focuses on the IRRO cancellation with the aid of the spintorque memristor technology. Spin-torque memristors in series, compared to parallel, show less resistance and process variations. The resistance value of a spin-torque memristor is regarded as frozen when the current flow over the spin-torque memristor is lower than its critical switching current value. In fact, the proposed structure employs a non-destructive sensing scheme in order to achieve a relatively large sense margin by reducing the IRRO. Our main idea is to reduce or eliminate the IRRO by exploiting the spin-torque memristors for providing the current matching on the input transistors of the voltage comparator. In particular, the overwrite problem of the spin-torque memristor is solved by setting the critical switching current of the spin-torque memristor to be greater than a current value corresponding to the maximum IRRO value. We evaluate the IRRO cancellation technique on the proposed comparator or sense amplifier using 45nm predictive CMOS technology. Although sense amplifiers are targeted in this study, our technique can be applied to any analog amplifier suffering from the IRRO.
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ÖgeSynthesis and Optimization of Switching Nanoarrays(IEEE, 2015) Morgul, Muhammed Ceylan ; Altun, Mustafa ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication EngineeringIn this paper, we study implementation of Boolean functions with crossbar nanoarrays where each crosspoint behaves as a switch. This study has two main parts “formulation” and “optimization”. In the first part of formulation, we investigate nanoarray based implementation methodologies in the literature. We classify them as two-terminal or four-terminal switch based. We generalize these methodologies to be applicable for any given Boolean function by offering array size formulations. In the second part of optimization, we focus on four-terminal switch based implementations; we propose a synthesis method to implement Boolean functions with optimal array sizes. Finally, we perform synthesis trials on standard benchmark circuits to evaluate the proposed optimal method in comparison with previous nanoarray based implementation methods. The proposed synthesis method gives by far the smallest array sizes and offers a new design paradigm for nanoarray based computing architectures.
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ÖgeSynthesis and Performance Optimization of a Switching Nano-crossbar Computer(IEEE, 2016) Alexandrescu, Dan ; Altun, Mustafa ; Anghel, Lorena ; Bernasconi, Anna ; Ciriani, Valentina ; Frontini, Luca ; Tahoori, Mehdi ; Elektronik ve Haberleşme Mühendisliği ; Electronics and Communication EngineeringBeyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to siliconbased devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new adhoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements both arithmetic and memory elements, necessitated by achieving a computer, by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of arithmetic and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of “Emerging Computing Models” or “Computational Nanoelectronics”, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS.