Bir Hücresel Yapay Sinir Ağının Sabit Noktalı Sayı Aritmetiğiyle Sayısal Tasarımı Ve Gerçeklenmesi

Abstract

Bu çalışmada, en kısa yolu bulma problemine çözüm üretebilen bir hücresel yapay sinir ağı tasarlanıp gerçeklenmektedir. Tasarlanan devre daha önceden kayan noktalı sayı aritmetiği kullanılarak gerçeklenmiştir. Bu tez çalışmasında ise sabit noktalı sayı aritmetiği kullanılarak gerçekleme yapılmaktadır. Sabit noktalı sayı aritmetiğini kullanmak kaynak kullanımı ve öykünleme hızı anlamında iyileştirmelere imkan sağlamaktadır. Çalışmanın içeriğinde ilk olarak hücresel yapay sinir ağları incelenmiştir. Hücre modeli olarak Relaksasyon Osilatörü temelli Hücresel Yapay Sinir Ağı (RO-HYSA) modeli kullanılmaktadır. Modele ilişkin benzetim sonuçları sabit noktalı sayı aritmetiği yardımıyla elde edilmiştir. Benzetimi yapılan 4x4 hücreli RO-HYSA, hedeflenen tasarım olan 128x128 hücreli programlanabilen RO-HYSA'nın temelini oluşturmaktadır. 4x4 hücreli ağ çoğaltılıp düzgün biçimde dizilerek 128x128 hücreli ağ oluşturulmaktadır. Ağın FPGA'da gerçeklenebilmesi için gerekli çevre birimler kullanılmakta ve ağ ile haberleştirilmektedir. Tasarım aşamasında kullanılacak sayı aritmetiği, sabit noktalı sayı aritmetiğidir. Bu aritmetiğin, kayan noktalı sayı aritmetiğine kıyasla FPGA üzerinde daha az yer kaplayacağı ve daha hızlı öykünleme gerçekleştireceği öngörülmüştür. Bu sayı aritmetiği, hücre modeline ilişkin durum değişken değerleri ve parametre değerleri düşünülerek tasarlanmış ve hücrenin matematiksel modelini gerçekleyecek devre içerisine gömülmüştür. Bu tasarım Xilinx Virtex-II Pro Development System devre kartındaki XC2VP30 FPGA'sında gerçeklenmiştir. Kayan noktalı sayı aritmetiği kullanılarak elde edilen dalga formlarının çoğu bu çalışma sonucunda da gözlenmiştir. Sonuç olarak, sabit noktalı sayı aritmetiği ile tasarlanan HYSA'nın FPGA üzerinde gerçeklenmesinin daha az kaynak kullanımı ve daha yüksek öykünleme hızı ile kayan noktalı olarak tasarlanan aynı boyuttaki ağ ile benzer uzay-zaman dalgaları ürettiği gözlenmiştir. Tezde önerilen tasarım ve gerçeklemeler en kısa yol bulma gibi uzay-zaman dalgalarını kullanan uygulamalarda uzay-zaman dalgalarının yüksek hızda üretiminde kullanmak için uygundur.

In this thesis, a cellular neural network that solves the shortest path finding problem is designed and implemented. The designed circuit has been implemented using floating-point number arithmetic previously. In this study, the implementation is performed by using fixed-point number arithmetic. Using fixed-point number arithmetic enables some improvements in the meaning of source utilization and speed of emulation. In the content of study, first of all cellular neural network has been researched. The architecture of CNN consists of rectangular cell arrays which are in the mxn form. The minimal unit of the architecture is called "cell". These cells are placed to two dimensional space in form of cartesian coordinate system where m means the number of rows and n means the number of column. C(i,j) is called the cell that it is in the i. row and j. column. Relaxation Oscillator based Cellular Neural Network (RO-CNN) model is used as model of the cell. In literature, active waves are producted by using this model and some important engineering applications such as path planning and robot navigation are implemented by using these waves. Computer simulation results of the chosen model is analyzed by using fixed-point number arithmetic. 4x4 cellular RO-CNN that is simulated network forms a basis of targeted design of 128x128 cellular programmable RO-CNN. 128x128 cellular network is composed by enhancing and collating the 4x4 cellular network in a formal shape. In order to implement this network on an FPGA, environmental units are required and these units are communicated with the network. In this thesis, the main focus is to design an alternative RO-CNN with fixed-point number arithmetic among to Yeniceri's study and to observe the same waveforms. Number representation format that is used on the design stage is fixed-point number arithmetic. Fixed-point number arithmetic is symbolized as Qm.n. In this format, m means the whole part of the number and n means the fractional part of the number in decimal. State variables, initial condition values and values of parameters used on the model are in 16-bit width. Therefore, number arithmetic will be used is Q6.9 where 1 bit is for sign. Designed arithmetic has been predicted that consumes less sources of FPGA and performs faster emulation in comparison with floating-point number arithmetic since the very beginning of the study. The arithmetic is embedded inside the circuit that realizes the mathematical model of the cell. In order to compute new values of the state variables, the mathematical model of the network has summation and multiplication circuits. Designed summation circuit sums two fixed-point numbers in 2 clock cycle. On the other hand, summation circuit that is designed using floating-point arithmetic needs 9 times more cycle. Also summation circuit consumes %90 fewer resource on the implementation stage. Multiplication circuit with fixed-point arithmetic gives the answer in 2 clock cycle as the floating-point multiplication circuit gives. However, multiplication circuit consumes %80 fewer resource on the implementation stage. Neural Processing Element (NPE) is the most important unit of the CNN circuit that perform the function of the cell. NPE has registers of the requested computation values but does not keep any value of nework constantly. NPEs is used to get a matrix by obtained themselves in order to make network have parallel processing ability. 4x4 parallel processing units are obtained from these NPEs for 128x128 cellular network. Cellular Neural Processing Network (CNPN) has 16 NPEs that execute an iteration parallelly. One of the most important duty of the CNPN is to make NPEs begin the iteration and make NPEs finish the iteration. Other one is to deliver parameters, state variables and initial conditions to related NPEs. CNN emulator digital circuit that is called Wave Computer Core insists on Control Circuit, Parameter Register, Communication Circuit, VGA Driver Circuit, CNPN Circuit and RAM network. The most important duties of the Control Circuit is to make CNPN begin and finish the iteration, RAM read the new values and write the computed values of the network, Parameter Register read and write the values of the network, Communication Circuit and VGA Driver Circuit to operate in order to get network image on the on-line monitor VGA. New core circuit with fixed-point number arithmetic consumes approximately %28 fewer resource on the implementation stage rather than core circuit with floating-point number arithmetic. The number of used BlockRAM is the same in two studies. All design is called Autowave Generator (AWG) and new AWG design is faster than previous design because of used fixed-point number arithmetic in NPE Circuit. New AWG design consumes approximately %19 fewer slices of logic, %21 FlipFlop, %21 Look-up-Table and %36 MULT18x18 multiplier element on the FPGA. This design is implemented on XC2VP30 FPGA chip that is inside Xilinx Virtex-II Pro Development System board. In order to transfer parameters, state variables and initial conditions from controller computer to FPGA, RS-232 communication serial port is used and this port is programmed by using MATLAB platform in computer. When the all design is obtained and programmed by using Xilinx ISE platform, file of the implementation code is generated. Programming file is transferred from controller computer to the FPGA by using Xilinx IMPACT programming platform. After programming the FPGA, parameters, state variables and initial conditions are transferred to the FPGA and designed core begins the iteration with control signals. While network is emulated, obtained network image can be watched on the VGA monitor. Therefore, wave forms that are obtained by using floating-point number arithmetic are also observed in this study. All implementation results are compared with previous study. New AWG design is faster than the previous. Therefore, bigger size cellular network can be obtained and implement on the same FPGA. Used number of BlockRAM is the same as previous. So, for bigger size cellular network implementation, external memory may be needed. As a result, minor resource utilization and higher emulation speed of implementation on FPGA of the CNN that is designed with fixed-point number arithmetic and same sized network designed with floating-point arithmetic were observed that similar spatiotemporal waves are generated. Design and implementations proposed in this thesis is suitable for using in finding the shortest path applications where high speed propagation of spatiotemporal waves is needed.