Multiple-valued static CMOS memory cell

Abstract

The conventional flip-flop core is generalized to multistability in full static CMOS without compromising the standard binary CMOS features such as ratioless device sizing, negligible static power consumption, and wide noise margins. The proposed multiple-level cell is built with eight devices for three-level operation and necessitates four more devices for each additional level. It can be arranged with a proper address scheme to function as a RAM cell, D-latch, or synaptic memory. Experimental work verifies four-level operation with 3-V supply. Simulations indicate the possibility of six-level storage in 5-V operation. The cell retains noise margins one threshold voltage wide even at such high-level operation. This is made possible by exploiting the dynamic hysteresis associated with the transfer characteristic of an inverter operating with very low rail-to-rail voltage.