MOS-only polyphase filter with small chip area

Abstract

In this paper, it is aimed to realize a systematic approach for the realization of the MOS only complex polyphase filters which occupy small chip area. For this purpose, we used a technique based on adding cross-coupled transistors realizing local positive feedback, which, in turn, increases filter time constants. Thanks to this method, a substantial reduction in the filter chip area is achieved without having to use bulky on chip capacitors. The usefullness of the approach is validated by comparing the layouts of the designed CMOS circuit with the conventional RC polyphase filter. Post-layout simulation results using SPECTRE in CADENCE design environment are provided to verify feasibility of the proposed complex filter.