A High Performance TIA Design in 40 nm CMOS

Abstract

In optical communication systems, transimpedance amplifiers (TIAs) play a critical role as they are used in the front end of receivers to sense the optical inputs thereby converting them into electrical signals. In this paper, a low noise, high gain, and low power TIA is presented in 40 nm CMOS technology. To compensate for the low intrinsic gain of the technology, a structure, which comprises a shunt-shunt feedback amplifier for the first stage and two post-amplifiers for the following stages are designed. Active inductive loads are employed to extend the bandwidth. Post-layout simulation results show that the designed TIA has a bandwidth over 5 GHz, a transimpedance gain 75 dBΩ, and an input-referred noise current in bandwidth less than 8 pA/√Hz. The total layout occupies a chip estate of 0.0052 mm2 while the DC power consumption is found to be 7.15 mW without the output buffer, using a single 1.1 V power supply.