Design and Optimization of Multiple-Channel Double Dynamic Switching Biased Op-Amp for Switched Capacitor Integrator Using FinFET Technology

Abstract

This paper presents the design and optimization of a parametric multiple-channel Double Dynamic Switching Biased Complementary Folded-Cascode Amplifier with switched capacitor integrator application in 32nm FinFET technology. The LTspice simulations demonstrate that the amplifier can attain an open-loop DC gain of 44.8dB, and a phase margin of about 87.8 degrees with +/- 0.5V supply voltages. Moreover, the amplifier power consumption is measured 246 mu W including bias circuitry and a Gain-Bandwidth Product (GBW) of 77.45MHz under a 5pF load capacitor.The circuit's stability enables it to offer diverse design capabilities tailored to specific application needs. This novel design is capable of reducing supply voltages and power dissipation.