A switchable DC offset cancellation circuit for time-based degradation correction

Abstract

This paper focuses on observing the aging impact of a DC offset cancellation circuit (DCOC) on the performance of an amplifier subject to time-based degradation, also known as aging. The circuit can be activated or deactivated to reduce the offset voltage that arises due to possible mismatches between the aging transistor in an amplifier. The proposed DCOC is designed along with a fully differential amplifier. It is fabricated in the low power TSMC 40 nm CMOS technology by using a single power supply of 1.1 V. Post-layout simulation results demonstrate that the offset suppression can be realized both in the Monte Carlo (MC) and corner analysis. In the measurement results of the fabricated chips, the DC offset, which is present before the deactivation of the DCOC, is suppressed by 19.25 dB.