A tunable lossy grounded capacitance multiplier circuit based on VDTA for the low frequency operations

Abstract

Capacitors occupy very large area on chips. To reduce the occupation area on chip for circuits employing large capacitances, capacitance multipliers are used. In this work, a new design of Voltage Differencing Transconductance Amplifier based capacitance multiplier and its CMOS implementation are proposed. The multiplication factor of the proposed circuit can be electronically tunable between 115 and 150. The design of the proposed grounded capacitor multiplier is verified with the simulations in Cadence environment with 0.18 mu m TSMC technology. Also, Monte-Carlo analysis and temperature behavior are investigated under post-layout realization of the proposed multipler circuit (27.58 mu m x 44.68 mu m). Taken into consideration with respect to counterparts studies in the literature, proposed architecture gives promising results under different operating conditions for the low frequency applications.