Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates

Abstract

In reversible circuits, a fault as a change in logic value at a circuit node always alters an output logic value, so observability of faults at the output is 100%. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible circuits to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED). For this purpose we propose a new, fault preservative, and reversible gate library called Even Target Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPCT, we ensure that the parity, even or odd, is preserved at all levels including the output level unless there is a faulty node. Our design strategy has two steps for a reversible function: 1) implement the reversible functions with the ET-MPMCT library; and 2) apply reversible-to-CMOS gate conversion. In case an irreversible function needs to be synthesized then its reversible form is used followed by the two design steps. As a result, we have come up with a CMOS circuit having 100% CED. The performance of our approach is compared with other CED schemes in the literature in terms of area, detection rate, and power consumption. Simulations are done with Cadence Genus tool using TSMC $0.18 \mu \mathrm{m}$ technology. Clearly, results are in favor of our proposed technique.