Analysis Of Superlu Solvers On Intel® Mic Architecture

Abstract

Intel Xeon Phi is a coprocessor with sixty-one cores in a single chip. The chip has a more powerful FPU that contains 512-bit<br> SIMD registers. Intel Xeon Phi chip can benefit from the algorithms that operate with the large vectors. In this work, sequential,<br> multithreaded and distributed versions of SuperLU solvers are tested on the Intel Xeon Phi using offload programming model<br> and they work well. There are several offload programming alternatives depending on where to place pragma directives. We find<br> that the sequential SuperLU benefited up to 45% performance improvement from the offload programming depending on the<br> sparse matrix type and the size of transferred and processed data. On the other hand, the partitioning method of SuperLU_DIST<br> and SuperLU_MT generates very small sized submatrices. Therefore, we observe that the matrix partitioning method and several<br> other tradeoffs influence their performance via the Xeon Phi architecture.