A compact monitoring circuit for real-time on-chip diagnosis of hot-carrier induced degradation

Abstract

A very simple test/monitor circuit is presented which emulates the hot-carrier induced degradation of those critical circuits which are most susceptible to hot-carrier induced aging in a large system on chip. Delay-time degradation, as opposed to current degradation, is devised as a more realistic measure for monitoring long-term circuit reliability, and a simple method is presented for measuring this degradation. The hot-carrier aging monitor is capable of issuing a warning signal (flag) when the amount of hot-carrier induced transient performance degradation in critical circuits on the chip exceeds a pre-determined limit value. The monitor circuitry occupies a very small silicon area; and it can be added to any large-scale design with a minimum of extra cost, at the end of the design cycle.