Robust design and yield enhancement of low-voltage CMOS analog integrated circuits

Abstract

Basic CMOS low-voltage analog cells are introduced and used in the design of low-voltage CMOS multipliers. A statistical design flow for enhancing the parametric functional yield of these low-voltage circuits, with the goal of achieving a robust performance, is described. The design flow is based on using the response surface methodology (RSM) and design of experiments (DOE) techniques as statistical VLSI design techniques together with the statistical MOS (SMOS) model. Offset and nonlinearity performances are statistically examined. The response surfaces show the trade-off between area and functional yield. Using these surface contours, the designer will be able to estimate the functional yield of the circuits before fabrication. The contours are also used in the statistical optimization of device sizes as they provide information regarding which transistor aspect ratios are to be altered to achieve a better functional yield.