Linear transconductors using low voltage low power square-law CMOS cells

Abstract

Two transconductors composed of two square-law CMOS cells are introduced in this paper. The analysis of the cells is given. The transconductors operate in the saturation region with a fully balanced input signal. Simulations were done for 0.8 /spl mu/m n-well process using BSIM3 model parameters. The first circuit has a trade-off between low voltage operation and low power dissipation. The circuit has a cutoff frequency of 170 MHz and P/sub dis/=1.17 mW for a bias current of 120 /spl mu/A. The second transconductor has aimed to overcome the trade-off and to improve the performance; the circuit has a cutoff frequency of 236 MHz and P/sub dis/=1.74 mW for the same bias current; however, it is possible to reduce the bias current, since the trade-off the transconductors have a THD of less then -56 dB and -60 dB, respectively, for 1 MHz, 0.5 V peak-to-peak sinusoidal input. A comparison between the two circuit performances is given.