9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits

Abstract

An algorithm for generating test patterns for combinational circuits has been developed and programmed. The algorithm is definitive and finds a test for all faults including those that require multiple paths to be sensitized, by sensitizing a single path at a time and trying at most each single path. This is achieved by using a new calculus based on nine values (0,1,D,D,0/D,0/D, 1/D,1/D,U). One path is deliberately sensitized while the alternative paths are assigned values which permit the option of desensitizing or sensitizing them as the sensitized path is developed. Experimental results are presented for a variety of cases.