A Hardware Accelerated Packet Classifier Design for A Network Router

Abstract

In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classification functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has %15 faster clock speed than similar works.