Design of a cmos feedforward automatic gain control system for optical front-ends

Abstract

This thesis presents the design of a high-compression feedforward Automatic Gain Control (AGC) system generated for optical front-ends operating at 1 Gbps PAM-4 modulation over Plastic Optical Fiber (POF) and Visible Light Communication (VLC). Since the amplitude of the input signal exhibits large variations in these applications, maintaining a stable output signal amplitude is crucial. The AGC system aims to ensure reliable signal processing under dynamic conditions. There are two different methods to apply AGC: feedforward and feedback AGC. This thesis chooses a feedforward methodology for the AGC system due to its fundamental advantages in speed and stability. This choice allows the system to react almost instantly to changes in signal strength. It achieves sub-microsecond attack and release times in post-layout simulations. The primary benefit of the design is achieving a high compression ratio of approximately 30 dB. The AGC system controls the gain of a variable-gain transimpedance amplifier (VG-TIA) by utilizing secondary circuits that sense the signal amplitude and generate the required voltages. In detail, the main building blocks of the AGC include a variable-gain transimpedance amplifier (VG-TIA), a peak detector, a current-mode Flash analog-to-digital converter (ADC), and a control voltage generation (CVG) circuit. A CMOS inverter with resistive feedback topology is employed in the TIA design. The VG-TIA supports both coarse and fine gain control through switched resistors and triode-region transistors, respectively. Since the gain is changing with respect to the amplitude, the signal level should be examined. For this purpose, a high-dynamic-range peak detector has been designed. The peak detector accurately measures the input signal amplitude with minimal ripple, ensuring fast and reliable gain updates. The ADC compares the mirrored input current against reference currents from a bandgap source to produce digital gain control signals. In parallel, the CVG circuit generates analog voltages proportional to the signal amplitude, which finely tune the TIA gain by adjusting the gates of triode-region transistors. The entire system is implemented in a commercial 65 nm CMOS process and operates from a 1.8 V supply. Post-layout simulation results indicate that the proposed AGC achieves a 32 dB gain adjustment while maintaining a bandwidth of over 700 MHz across all gain settings. The compression ratio is approximately 30 dB, and the attack and release times are around 250 ns. The design demonstrates its effectiveness as a fast, stable, and high-performance AGC solution for next-generation optical front-ends.