FBE- Elektronik Mühendisliği Lisansüstü Programı - Yüksek Lisans
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ÖgeStudies on the design of robust and fully-digital random number generators(Fen Bilimleri Enstitüsü, 2020) Acar, Burak ; Karalar, Tufan Coşkun ; 644352 ; Elektronik MühendisliğiThe random number generator is a module that produces unpredictable bit sequences with various statistical properties. Multiple tools such as dice and metal coins have been used since ancient times to make random choices. Today, even in a football game, a coin is used to decide which team will start the game. Random number generation is one of today's popular topics in information security. Random Number Generators (RNGs) are at the core of cryptosystems with producing unpredictable secret keys. The weaknesses of the random number generator of a cryptosystem can cause confidential data to fall into undesirable third parties' hands. Therefore, random number generation mechanisms should be based on physical entropy sources. RNGs are used not only for cryptography but also in Monte Carlo simulations, learning algorithms, science, art, gaming, scrambling, etc. Random number generators are classified into two main groups, Pseudo Random Number Generators (PRNGs) and True Random Number Generators (TRNGs). PRNGs generate new values from seed using certain functions. These bit sequences, which have a statistically random appearance, repeat themselves after a certain period of time. Therefore, the generated bit sequences are periodic and predictable. On the other hand, true random number generators use physical quantities as an entropy source. They generate random numbers that do not repeat themselves, where the generated bit is independent of the previous bit. Random number generators can be implemented using software or hardware. Hardware based random number generators can be implemented on an FPGA platform or ASIC chip. Designers prefer FPGA platforms because of their features, such as rapid prototyping, reprogrammable, low production cost. Besides, FPGA platforms have low noise sources since they are designed to work in digital circuits. Therefore, generating random numbers on an FPGA requires some design requirements. The designs made as ASIC allow the entropy source to be designed with the desired features more easily. ASIC designs are more preferred in designs to be mass-produced due to their high production costs and high design costs. Random number generators are designed on FPGA or ASIC according to the desired features and application restrictions. In this study, some state-of-the-art designs of TRNGs especially implemented digitally are examined, and some new improvements and design techniques are proposed. First of all, a three-dimensional no-equilibrium chaos-based RNG published in the literature is implemented on an FPGA. The master-slave synchronization method is tried to be achieved by implementing a clone of the target circuit on the FPGA. Although the initial conditions of the attacked circuit are unknown, it is experimentally shown that the same bit sequence can be produced in the clone circuit as a result of listening to an output of the attack circuit. Thus, it is shown that RNGs based on deterministic sources are vulnerable to possible attacks and should not be used without any noise source. A ring oscillator-based random number generator cannot be used in applications requiring low power consumption due to their high power consumption. For low power consumption, a random number generation technique is proposed by engaging and disengaging SR latch structures at specified intervals. The fact that the digital gates used are active only at certain times and require fewer digital gates has reduced power consumption. Immunity of the SR latch structure against correlation-based attacks was investigated in the earlier studies. The method of sampling this structure at irregular time was also proposed in the previous studies. In this study, an ASIC version of these structures is explained. A fully digital random number generator with low power consumption, which can be used for different applications of different chips, is designed as an ASIC in TSMC 180 nm technology. The created custom IP occupies 120 μm * 114 μm. This study is important for summarizing current works in digital random number generators, for comparing their security and performance.